Advanced use case - Peripheral Bus Clock Management (UC3B0/UC3B1)

Advanced use case - Peripheral Bus Clock Management (UC3B0/UC3B1)

This section will present a more advanced use case for the System Clock Management service. This use case will configure the main system clock to 48MHz, using an internal PLL module to multiply the frequency of a crystal attached to the microcontroller. The peripheral bus clocks will be divided down by a factor of two, and the USB clock will be configured via a separate PLL module.

Prerequisites

• None

Initialization code

Add to the application initialization code:

sysclk_init();

Workflow

1. Configure the system clocks according to the settings in conf_clock.h:

   sysclk_init(); 

Example code

Add or uncomment the following in your conf_clock.h header file, commenting out all other definitions of the same symbol(s):

#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL0

// Fpll0 = (Fclk * PLL_mul) / PLL_div
#define CONFIG_PLL0_SOURCE          PLL_SRC_OSC0
#define CONFIG_PLL0_MUL             (48000000UL / BOARD_OSC0_HZ)
#define CONFIG_PLL0_DIV             1

// Fbus = Fsys / (2 ^ BUS_div)
#define CONFIG_SYSCLK_CPU_DIV       0
#define CONFIG_SYSCLK_PBA_DIV       1
#define CONFIG_SYSCLK_PBB_DIV       1

#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL1

// Fpll1 = (Fclk * PLL_mul) / PLL_div
#define CONFIG_PLL1_SOURCE          PLL_SRC_OSC0
#define CONFIG_PLL1_MUL             (48000000UL / BOARD_OSC0_HZ)
#define CONFIG_PLL1_DIV             1

// Fusb = Fsys / USB_div
#define CONFIG_USBCLK_DIV           1

Workflow

1. Configure the main system clock to use the output of the PLL0 module as its source:

   #define CONFIG_SYSCLK_SOURCE           SYSCLK_SRC_PLL0 

2. Configure the PLL0 module to use external crystal oscillator OSC0 as its source:

   #define CONFIG_PLL0_SOURCE             SYSCLK_SRC_OSC0 

3. Configure the PLL0 module to multiply the external oscillator OSC0 frequency up to 48MHz:

   #define CONFIG_PLL0_MUL              (48000000UL / BOARD_OSC0_HZ)
   #define CONFIG_PLL0_DIV              1 

   Note

   For user boards, BOARD_OSC0_HZ should be defined in the board conf_board.h configuration file as the frequency of the crystal attached to OSC0.

4. Configure the main clock to run at the full 48MHz, scale the peripheral busses to run at one half (2 to the power of 1) of the system clock speed:

   #define CONFIG_SYSCLK_CPU_DIV       0
   #define CONFIG_SYSCLK_PBA_DIV       1
   #define CONFIG_SYSCLK_PBB_DIV       1

   Note

   Some dividers are powers of two, while others are integer division factors. Refer to the formulas in the conf_clock.h template commented above each division define.

5. Configure the USB module clock to use the output of the PLL1 module as its source:

   #define CONFIG_USBCLK_SOURCE           USBCLK_SRC_PLL1 

6. Configure the PLL1 module to use external crystal oscillator OSC0 as its source:

   #define CONFIG_PLL1_SOURCE             SYSCLK_SRC_OSC0 

7. Configure the PLL1 module to multiply the external oscillator OSC0 frequency up to 48MHz:

   #define CONFIG_PLL1_MUL              (48000000UL / BOARD_OSC0_HZ)
   #define CONFIG_PLL1_DIV              1

8. Configure the USB module to perform no division on the input clock speed:

   #define CONFIG_USBCLK_DIV              1