Usage

Translation Look-aside Buffers (TLBs) are an implementation technique that caches translations or translation table entries. TLBs avoid the requirement for every memory access to perform a translation table lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a similar way to the requirements for caches, the architecture only defines certain principles for TLBs:

The MMU supports memory accesses based on memory sections or pages: Super-sections Consist of 16MB blocks of memory. Support for Super sections is optional.

1. Sections Consist of 1MB blocks of memory.
2. Large pages Consist of 64KB blocks of memory.
3. Small pages Consist of 4KB blocks of memory.

Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry. Memory region attributes Each TLB entry has an associated set of memory region attributes. These control accesses to the caches, how the write buffer is used, and if the memory region is Shareable and therefore must be kept coherent.

Related files:
mmu.c
mmu.h