Synchronous Serial Controller (SSC) driver for SAM.
Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
| #define | SSC_TCMR_START_TF_EDGE SSC_TCMR_START_RF_EDGE |
| #define | SSC_TCMR_START_TF_FALLING SSC_TCMR_START_RF_FALLING |
| #define | SSC_TCMR_START_TF_RISING SSC_TCMR_START_RF_RISING |
| #define | SSC_WPMR_WPKEY_PASSWD SSC_WPMR_WPKEY(0x535343) |
Functions | |
| void | ssc_disable_interrupt (Ssc *p_ssc, uint32_t ul_sources) |
| Disable SSC interrupts. More... | |
| void | ssc_disable_rx (Ssc *p_ssc) |
| Disable SSC receiver. More... | |
| void | ssc_disable_tx (Ssc *p_ssc) |
| Disable SSC Transmitter. More... | |
| void | ssc_disable_tx_frame_sync_data (Ssc *p_ssc) |
| The TD line is driven with the default value during the Transmit Frame Sync signal. More... | |
| void | ssc_enable_interrupt (Ssc *p_ssc, uint32_t ul_sources) |
| Enable SSC interrupts. More... | |
| void | ssc_enable_rx (Ssc *p_ssc) |
| Enable SSC receiver. More... | |
| void | ssc_enable_tx (Ssc *p_ssc) |
| Enable SSC Transmitter. More... | |
| void | ssc_enable_tx_frame_sync_data (Ssc *p_ssc) |
| The TD line is driven with the SSC_TSHR register value during the transmission of the Transmit Frame Sync Signal. More... | |
| uint32_t | ssc_get_interrupt_mask (Ssc *p_ssc) |
| Read SSC interrupt mask. More... | |
| Pdc * | ssc_get_pdc_base (Ssc *p_ssc) |
| Get SSC PDC registers base address. More... | |
| void * | ssc_get_rx_access (Ssc *p_ssc) |
| Get Receive address for DMA operation. More... | |
| uint32_t | ssc_get_rx_compare (Ssc *p_ssc, uint32_t ul_id) |
| Get SSC Receive Compare Register. More... | |
| uint32_t | ssc_get_status (Ssc *p_ssc) |
| Read SSC status. More... | |
| void * | ssc_get_tx_access (Ssc *p_ssc) |
| Get Transmit address for DMA operation. More... | |
| uint32_t | ssc_get_writeprotect_status (Ssc *p_ssc) |
| Indicate write protect status. More... | |
| void | ssc_i2s_set_receiver (Ssc *p_ssc, uint32_t ul_mode, uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen) |
| Setup for I2S receiver. More... | |
| void | ssc_i2s_set_transmitter (Ssc *p_ssc, uint32_t ul_mode, uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen) |
| Setup for I2S transmitter. More... | |
| uint32_t | ssc_is_rx_buf_end (Ssc *p_ssc) |
| Check if one receive buffer is filled. More... | |
| uint32_t | ssc_is_rx_buf_full (Ssc *p_ssc) |
| Check if both receive buffers are full. More... | |
| uint32_t | ssc_is_rx_enabled (Ssc *p_ssc) |
| Check if receiver is enabled. More... | |
| uint32_t | ssc_is_rx_ready (Ssc *p_ssc) |
| Check if data has been received and loaded in SSC_RHR. More... | |
| uint32_t | ssc_is_tx_buf_empty (Ssc *p_ssc) |
| Check if both transmit buffers are empty. More... | |
| uint32_t | ssc_is_tx_buf_end (Ssc *p_ssc) |
| Check if the register SSC_TCR has reached 0. More... | |
| uint32_t | ssc_is_tx_empty (Ssc *p_ssc) |
| Check if the last data written in SSC_THR has been loaded in TSR and the last data loaded in TSR has been transmitted. More... | |
| uint32_t | ssc_is_tx_enabled (Ssc *p_ssc) |
| Check if transmitter is enabled. More... | |
| uint32_t | ssc_is_tx_ready (Ssc *p_ssc) |
| Check if data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). More... | |
| uint32_t | ssc_read (Ssc *p_ssc, uint32_t *ul_data) |
| Read from SSC Receive Holding Register. More... | |
| uint32_t | ssc_read_sync_data (Ssc *p_ssc) |
| Read from SSC Receive Synchronization Holding Register. More... | |
| void | ssc_reset (Ssc *p_ssc) |
| Reset SSC module. More... | |
| uint32_t | ssc_set_clock_divider (Ssc *p_ssc, uint32_t ul_bitrate, uint32_t ul_mck) |
| Set up clock. More... | |
| void | ssc_set_loop_mode (Ssc *p_ssc) |
| Configure SSC to work in loop mode. More... | |
| void | ssc_set_normal_mode (Ssc *p_ssc) |
| Configure SSC to work in normal mode. More... | |
| void | ssc_set_receiver (Ssc *p_ssc, clock_opt_t *p_rx_clk_opt, data_frame_opt_t *p_rx_data_frame) |
| Configure SSC receiver clock mode and date frame configuration. More... | |
| void | ssc_set_rx_compare (Ssc *p_ssc, uint32_t ul_id, uint32_t ul_value) |
| Configure SSC Receive Compare Register. More... | |
| void | ssc_set_rx_stop_selection (Ssc *p_ssc, uint32_t ul_sel) |
| Configure SSC receive stop selection. More... | |
| void | ssc_set_td_default_level (Ssc *p_ssc, uint32_t ul_level) |
| Configure SSC default level driven on the TD pin while out of transmission. More... | |
| void | ssc_set_transmitter (Ssc *p_ssc, clock_opt_t *p_tx_clk_opt, data_frame_opt_t *p_tx_data_frame) |
| Configure SSC transmitter clock mode and date frame configuration. More... | |
| void | ssc_set_writeprotect (Ssc *p_ssc, uint32_t ul_enable) |
| Enable or disable write protection of SSC registers. More... | |
| uint32_t | ssc_write (Ssc *p_ssc, uint32_t ul_frame) |
| Write to SSC Transmit Holding Register. More... | |
| void | ssc_write_sync_data (Ssc *p_ssc, uint32_t ul_frame) |
| Write to SSC Transmit Synchronization Holding Register. More... | |
1.8.5