Microchip® Advanced Software Framework

Extra Information for SYSTEM CLOCK Driver

Acronyms

Below is a table listing the acronyms used in this module, along with their intended meanings.

Acronym Description
DFLL Digital Frequency Locked Loop
MUX Multiplexer
OSC32K Internal 32KHz Oscillator
OSC8M Internal 8MHz Oscillator
PLL Phase Locked Loop
OSC Oscillator
XOSC External Oscillator
XOSC32K External 32KHz Oscillator
AHB Advanced High-performance Bus
APB Advanced Peripheral Bus
DPLL Digital Phase Locked Loop

Dependencies

This driver has the following dependencies:

  • None

Errata

  • This driver implements experimental workaround for errata 9905

    "The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device." This driver will enable and configure the DFLL before the ONDEMAND bit is set.

Module History

An overview of the module history is presented in the table below, with details on the enhancements and fixes made to the module since its first release. The current version of this corresponds to the newest version in the table.

Changelog
Fixed system_gclk_chan_disable() deadlocking if a channel is enabled and configured to a failed/not running clock generator
  • Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from true to false
  • Fixed system_flash_set_waitstates() failing with an assertion if an odd number of wait states provided
  • Updated DFLL configuration function to implement workaround for errata 9905 in the DFLL module
  • Updated system_clock_init() to reset interrupt flags before they are used
  • Fixed system_clock_source_get_hz() to return correcy DFLL frequency number
  • Fixed system_clock_source_is_ready not returning the correct state for SYSTEM_CLOCK_SOURCE_OSC8M
  • Renamed the various system_clock_source_*_get_default_config() functions to system_clock_source_*_get_config_defaults() to match the remainder of ASF
  • Added OSC8M calibration constant loading from the device signature row when the oscillator is initialized
  • Updated default configuration of the XOSC32 to disable Automatic Gain Control due to silicon errata
Initial Release