Below is a table listing the acronyms used in this module, along with their intended meanings.
Acronym | Description |
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DFLL | Digital Frequency Locked Loop |
MUX | Multiplexer |
OSC32K | Internal 32KHz Oscillator |
OSC8M | Internal 8MHz Oscillator |
PLL | Phase Locked Loop |
OSC | Oscillator |
XOSC | External Oscillator |
XOSC32K | External 32KHz Oscillator |
AHB | Advanced High-performance Bus |
APB | Advanced Peripheral Bus |
DPLL | Digital Phase Locked Loop |
This driver has the following dependencies:
This driver implements experimental workaround for errata 9905
"The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device." This driver will enable and configure the DFLL before the ONDEMAND bit is set.
An overview of the module history is presented in the table below, with details on the enhancements and fixes made to the module since its first release. The current version of this corresponds to the newest version in the table.
Changelog |
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Fixed system_gclk_chan_disable() deadlocking if a channel is enabled and configured to a failed/not running clock generator |
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Initial Release |