Microchip® Advanced Software Framework

MUX Settings

The following lists the possible internal SERCOM module pad function assignments for the four SERCOM pads in both SPI Master and SPI Slave modes.

They are combinations of DOPO and DIPO in CTRLA. Note that this is in addition to the physical GPIO pin MUX of the device, and can be used in conjunction to optimize the serial data pin-out.

Master Mode Settings

The following table describes the SERCOM pin functionalities for the various MUX settings, whilst in SPI Master mode.

Note
If MISO is unlisted, the SPI receiver must not be enabled for the given MUX setting.
Combination DOPO / DIPO SERCOM PAD[0] SERCOM PAD[1] SERCOM PAD[2] SERCOM PAD[3]
A 0x0 / 0x0 MOSI SCK - -
B 0x0 / 0x1 MOSI SCK - -
C 0x0 / 0x2 MOSI SCK MISO -
D 0x0 / 0x3 MOSI SCK - MISO
E 0x1 / 0x0 MISO - MOSI SCK
F 0x1 / 0x1 - MISO MOSI SCK
G 0x1 / 0x2 - - MOSI SCK
H 0x1 / 0x3 - - MOSI SCK
I 0x2 / 0x0 MISO SCK - MOSI
J 0x2 / 0x1 - SCK - MOSI
K 0x2 / 0x2 - SCK MISO MOSI
L 0x2 / 0x3 - SCK - MOSI
M 0x3 / 0x0 MOSI - - SCK
N 0x3 / 0x1 MOSI MISO - SCK
O 0x3 / 0x2 MOSI - MISO SCK
P 0x3 / 0x3 MOSI - - SCK

Slave Mode Settings

The following table describes the SERCOM pin functionalities for the various MUX settings, whilst in SPI Slave mode.

Note
If MISO is unlisted, the SPI receiver must not be enabled for the given MUX setting.
Combination DOPO / DIPO SERCOM PAD[0] SERCOM PAD[1] SERCOM PAD[2] SERCOM PAD[3]
A 0x0 / 0x0 MISO SCK /SS -
B 0x0 / 0x1 MISO SCK /SS -
C 0x0 / 0x2 MISO SCK /SS -
D 0x0 / 0x3 MISO SCK /SS MOSI
E 0x1 / 0x0 MOSI /SS MISO SCK
F 0x1 / 0x1 - /SS MISO SCK
G 0x1 / 0x2 - /SS MISO SCK
H 0x1 / 0x3 - /SS MISO SCK
I 0x2 / 0x0 MOSI SCK /SS MISO
J 0x2 / 0x1 - SCK /SS MISO
K 0x2 / 0x2 - SCK /SS MISO
L 0x2 / 0x3 - SCK /SS MISO
M 0x3 / 0x0 MISO /SS - SCK
N 0x3 / 0x1 MISO /SS - SCK
O 0x3 / 0x2 MISO /SS MOSI SCK
P 0x3 / 0x3 MISO /SS - SCK