Microchip® Advanced Software Framework

Configuration File Examples

conf_usb.h

UDI CDC Single

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _CONF_USB_H_
#define _CONF_USB_H_
#include "compiler.h"
#warning You must refill the following definitions with a correct values
#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL
#define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_ASF_MSC
#define USB_DEVICE_MAJOR_VERSION 1
#define USB_DEVICE_MINOR_VERSION 0
#define USB_DEVICE_POWER 100 // Consumption on VBUS line (mA)
#define USB_DEVICE_ATTR \
(USB_CONFIG_ATTR_SELF_POWERED)
// (USB_CONFIG_ATTR_BUS_POWERED)
// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED)
// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED)
// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name"
// #define USB_DEVICE_PRODUCT_NAME "Product name"
#define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC
#if (UC3A3||UC3A4)
//#define USB_DEVICE_HS_SUPPORT
#endif
// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high)
// extern void user_callback_vbus_action(bool b_vbus_high);
// #define UDC_SOF_EVENT() user_callback_sof_action()
// extern void user_callback_sof_action(void);
// #define UDC_SUSPEND_EVENT() user_callback_suspend_action()
// extern void user_callback_suspend_action(void);
// #define UDC_RESUME_EVENT() user_callback_resume_action()
// extern void user_callback_resume_action(void);
// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable()
// extern void user_callback_remotewakeup_enable(void);
// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable()
// extern void user_callback_remotewakeup_disable(void);
// #define UDC_GET_EXTRA_STRING()
#define UDI_MSC_GLOBAL_VENDOR_ID \
'A', 'T', 'M', 'E', 'L', ' ', ' ', ' '
#define UDI_MSC_GLOBAL_PRODUCT_VERSION \
'1', '.', '0', '0'
#define UDI_MSC_ENABLE_EXT() true
#define UDI_MSC_DISABLE_EXT()
#define UDI_MSC_NOTIFY_TRANS_EXT()
/*
* #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable()
* extern bool my_callback_msc_enable(void);
* #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable()
* extern void my_callback_msc_disable(void);
* #define UDI_MSC_NOTIFY_TRANS_EXT() msc_notify_trans()
* extern void msc_notify_trans(void) {
*/
#include "udi_msc_conf.h"
#endif // _CONF_USB_H_

UDI CDC Multiple (Composite)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _CONF_USB_H_
#define _CONF_USB_H_
#include "compiler.h"
#warning You must refill the following definitions with a correct values
#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL
#define USB_DEVICE_PRODUCT_ID 0xFFFF
#define USB_DEVICE_MAJOR_VERSION 1
#define USB_DEVICE_MINOR_VERSION 0
#define USB_DEVICE_POWER 100 // Consumption on VBUS line (mA)
#define USB_DEVICE_ATTR \
(USB_CONFIG_ATTR_SELF_POWERED)
// (USB_CONFIG_ATTR_BUS_POWERED)
// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED)
// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED)
// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name"
// #define USB_DEVICE_PRODUCT_NAME "Product name"
// #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC
//#define USB_DEVICE_LOW_SPEED
#if (UC3A3||UC3A4)
//#define USB_DEVICE_HS_SUPPORT
#endif
// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high)
// extern void user_callback_vbus_action(bool b_vbus_high);
// #define UDC_SOF_EVENT() user_callback_sof_action()
// extern void user_callback_sof_action(void);
// #define UDC_SUSPEND_EVENT() user_callback_suspend_action()
// extern void user_callback_suspend_action(void);
// #define UDC_RESUME_EVENT() user_callback_resume_action()
// extern void user_callback_resume_action(void);
// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable()
// extern void user_callback_remotewakeup_enable(void);
// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable()
// extern void user_callback_remotewakeup_disable(void);
// #define UDC_GET_EXTRA_STRING()
#define USB_DEVICE_EP_CTRL_SIZE 64
#define USB_DEVICE_NB_INTERFACE 1 // 1 or more
#define USB_DEVICE_MAX_EP 1 // 0 to max endpoint requested by interfaces
#define UDI_CDC_PORT_NB 1
#define UDI_CDC_ENABLE_EXT(port) true
#define UDI_CDC_DISABLE_EXT(port)
#define UDI_CDC_RX_NOTIFY(port)
#define UDI_CDC_TX_EMPTY_NOTIFY(port)
#define UDI_CDC_SET_CODING_EXT(port,cfg)
#define UDI_CDC_SET_DTR_EXT(port,set)
#define UDI_CDC_SET_RTS_EXT(port,set)
/*
* #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable()
* extern bool my_callback_cdc_enable(void);
* #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable()
* extern void my_callback_cdc_disable(void);
* #define UDI_CDC_RX_NOTIFY(port) my_callback_rx_notify(port)
* extern void my_callback_rx_notify(uint8_t port);
* #define UDI_CDC_TX_EMPTY_NOTIFY(port) my_callback_tx_empty_notify(port)
* extern void my_callback_tx_empty_notify(uint8_t port);
* #define UDI_CDC_SET_CODING_EXT(port,cfg) my_callback_config(port,cfg)
* extern void my_callback_config(uint8_t port, usb_cdc_line_coding_t * cfg);
* #define UDI_CDC_SET_DTR_EXT(port,set) my_callback_cdc_set_dtr(port,set)
* extern void my_callback_cdc_set_dtr(uint8_t port, bool b_enable);
* #define UDI_CDC_SET_RTS_EXT(port,set) my_callback_cdc_set_rts(port,set)
* extern void my_callback_cdc_set_rts(uint8_t port, bool b_enable);
*/
#define UDI_CDC_LOW_RATE
#define UDI_CDC_DEFAULT_RATE 115200
#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1
#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE
#define UDI_CDC_DEFAULT_DATABITS 8
#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_2 (4 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_2 (5 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_2 (6 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_3 (7 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_3 (8 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_3 (9 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_COMM_IFACE_NUMBER_0 0
#define UDI_CDC_DATA_IFACE_NUMBER_0 1
#define UDI_CDC_COMM_IFACE_NUMBER_2 2
#define UDI_CDC_DATA_IFACE_NUMBER_2 3
#define UDI_CDC_COMM_IFACE_NUMBER_3 4
#define UDI_CDC_DATA_IFACE_NUMBER_3 5
#define UDI_MSC_GLOBAL_VENDOR_ID \
'A', 'T', 'M', 'E', 'L', ' ', ' ', ' '
#define UDI_MSC_GLOBAL_PRODUCT_VERSION \
'1', '.', '0', '0'
#define UDI_MSC_ENABLE_EXT() true
#define UDI_MSC_DISABLE_EXT()
#define UDI_MSC_NOTIFY_TRANS_EXT()
/*
* #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable()
* extern bool my_callback_msc_enable(void);
* #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable()
* extern void my_callback_msc_disable(void);
* #define UDI_MSC_NOTIFY_TRANS_EXT() msc_notify_trans()
* extern void msc_notify_trans(void) {
*/
#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN)
#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT)
#define UDI_MSC_IFACE_NUMBER 0
#define UDI_HID_MOUSE_ENABLE_EXT() true
#define UDI_HID_MOUSE_DISABLE_EXT()
// #define UDI_HID_MOUSE_ENABLE_EXT() my_callback_mouse_enable()
// extern bool my_callback_mouse_enable(void);
// #define UDI_HID_MOUSE_DISABLE_EXT() my_callback_mouse_disable()
// extern void my_callback_mouse_disable(void);
#define UDI_HID_MOUSE_EP_IN (1 | USB_EP_DIR_IN)
#define UDI_HID_MOUSE_IFACE_NUMBER 0
#define UDI_HID_KBD_ENABLE_EXT() true
#define UDI_HID_KBD_DISABLE_EXT()
// #define UDI_HID_KBD_ENABLE_EXT() my_callback_keyboard_enable()
// extern bool my_callback_keyboard_enable(void);
// #define UDI_HID_KBD_DISABLE_EXT() my_callback_keyboard_disable()
// extern void my_callback_keyboard_disable(void);
#define UDI_HID_KBD_CHANGE_LED(value)
// #define UDI_HID_KBD_CHANGE_LED(value) my_callback_keyboard_led(value)
// extern void my_callback_keyboard_led(uint8_t value)
#define UDI_HID_KBD_EP_IN (1 | USB_EP_DIR_IN)
#define UDI_HID_KBD_IFACE_NUMBER 0
#define UDI_HID_GENERIC_ENABLE_EXT() true
#define UDI_HID_GENERIC_DISABLE_EXT()
#define UDI_HID_GENERIC_REPORT_OUT(ptr)
#define UDI_HID_GENERIC_SET_FEATURE(f)
/*
* #define UDI_HID_GENERIC_ENABLE_EXT() my_callback_generic_enable()
* extern bool my_callback_generic_enable(void);
* #define UDI_HID_GENERIC_DISABLE_EXT() my_callback_generic_disable()
* extern void my_callback_generic_disable(void);
* #define UDI_HID_GENERIC_REPORT_OUT(ptr) my_callback_generic_report_out(ptr)
* extern void my_callback_generic_report_out(uint8_t *report);
* #define UDI_HID_GENERIC_SET_FEATURE(f) my_callback_generic_set_feature(f)
* extern void my_callback_generic_set_feature(uint8_t *report_feature);
*/
#define UDI_HID_REPORT_IN_SIZE 64
#define UDI_HID_REPORT_OUT_SIZE 64
#define UDI_HID_REPORT_FEATURE_SIZE 4
#define UDI_HID_GENERIC_EP_SIZE 64
#define UDI_HID_GENERIC_EP_OUT (2 | USB_EP_DIR_OUT)
#define UDI_HID_GENERIC_EP_IN (1 | USB_EP_DIR_IN)
#define UDI_HID_GENERIC_IFACE_NUMBER 0
#define UDI_PHDC_ENABLE_EXT() true
#define UDI_PHDC_DISABLE_EXT()
#define UDI_PHDC_DATAMSG_FORMAT USB_PHDC_DATAMSG_FORMAT_11073_20601
#define UDI_PHDC_SPECIALIZATION {0x2345} // Define in 11073_20601
#define UDI_PHDC_QOS_OUT \
(USB_PHDC_QOS_MEDIUM_BETTER|USB_PHDC_QOS_HIGH_BEST)
#define UDI_PHDC_QOS_IN \
(USB_PHDC_QOS_LOW_GOOD|USB_PHDC_QOS_MEDIUM_BETTER|USB_PHDC_QOS_MEDIUM_BEST)
#define UDI_PHDC_METADATA_DESC_BULK_IN {0x01,0x02,0x03}
#define UDI_PHDC_METADATA_DESC_BULK_OUT {0x01,0x02,0x03}
#define UDI_PHDC_METADATA_DESC_INT_IN {0x01,0x02,0x03}
#define UDI_PHDC_EP_BULK_OUT (1 | USB_EP_DIR_OUT)
#define UDI_PHDC_EP_BULK_IN (2 | USB_EP_DIR_IN)
#if ((UDI_PHDC_QOS_IN&USB_PHDC_QOS_LOW_GOOD)==USB_PHDC_QOS_LOW_GOOD)
// Only if UDI_PHDC_QOS_IN include USB_PHDC_QOS_LOW_GOOD
# define UDI_PHDC_EP_INTERRUPT_IN (3 | USB_EP_DIR_IN)
#endif
#define UDI_PHDC_EP_SIZE_BULK_OUT 32
#define UDI_PHDC_EP_SIZE_BULK_IN 32
#define UDI_PHDC_EP_SIZE_INT_IN 8
#define UDI_PHDC_IFACE_NUMBER 0
#define UDI_VENDOR_ENABLE_EXT() true
#define UDI_VENDOR_DISABLE_EXT()
#define UDI_VENDOR_SETUP_OUT_RECEIVED() false
#define UDI_VENDOR_SETUP_IN_RECEIVED() false
/*
* #define UDI_VENDOR_ENABLE_EXT() my_callback_vendor_enable()
* extern bool my_callback_vendor_enable(void);
* #define UDI_VENDOR_DISABLE_EXT() my_callback_vendor_disable()
* extern void my_callback_vendor_disable(void);
*
* #define UDI_VENDOR_SETUP_OUT_RECEIVED() my_vendor_setup_out_received()
* extern bool my_vendor_setup_out_received(void);
* #define UDI_VENDOR_SETUP_IN_RECEIVED() my_vendor_setup_in_received()
* extern bool my_vendor_setup_in_received(void);
*/
#define UDI_VENDOR_EPS_SIZE_INT_FS 64
#define UDI_VENDOR_EPS_SIZE_BULK_FS 64
#define UDI_VENDOR_EPS_SIZE_ISO_FS 256
#define UDI_VENDOR_EPS_SIZE_INT_HS 64
#define UDI_VENDOR_EPS_SIZE_BULK_HS 512
#define UDI_VENDOR_EPS_SIZE_ISO_HS 64
#define UDI_VENDOR_EP_INTERRUPT_IN (1 | USB_EP_DIR_IN)
#define UDI_VENDOR_EP_INTERRUPT_OUT (2 | USB_EP_DIR_OUT)
#define UDI_VENDOR_EP_BULK_IN (3 | USB_EP_DIR_IN)
#define UDI_VENDOR_EP_BULK_OUT (4 | USB_EP_DIR_OUT)
#define UDI_VENDOR_EP_ISO_IN (5 | USB_EP_DIR_IN)
#define UDI_VENDOR_EP_ISO_OUT (6 | USB_EP_DIR_OUT)
#define UDI_VENDOR_IFACE_NUMBER 0
//... Eventually add other Interface Configuration
#define UDI_COMPOSITE_DESC_T
#define UDI_COMPOSITE_DESC_FS
#define UDI_COMPOSITE_DESC_HS
#define UDI_COMPOSITE_API
/* Example for device with cdc, msc and hid mouse interface
#define UDI_COMPOSITE_DESC_T \
usb_iad_desc_t udi_cdc_iad; \
udi_cdc_comm_desc_t udi_cdc_comm; \
udi_cdc_data_desc_t udi_cdc_data; \
udi_msc_desc_t udi_msc; \
udi_hid_mouse_desc_t udi_hid_mouse
#define UDI_COMPOSITE_DESC_FS \
.udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
.udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \
.udi_msc = UDI_MSC_DESC_FS, \
.udi_hid_mouse = UDI_HID_MOUSE_DESC
#define UDI_COMPOSITE_DESC_HS \
.udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
.udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \
.udi_msc = UDI_MSC_DESC_HS, \
.udi_hid_mouse = UDI_HID_MOUSE_DESC
#define UDI_COMPOSITE_API \
&udi_api_cdc_comm, \
&udi_api_cdc_data, \
&udi_api_msc, \
&udi_api_hid_mouse
*/
/* Example of include for interface
#include "udi_msc.h"
#include "udi_hid_kbd.h"
#include "udi_hid_mouse.h"
#include "udi_cdc.h"
#include "udi_phdc.h"
#include "udi_vendor.h"
*/
/* Declaration of callbacks used by USB
#include "callback_def.h"
*/
#endif // _CONF_USB_H_

conf_clock.h

XMEGA (USB)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_RCOSC
#define CONFIG_OSC_RC32_CAL 48000000UL
#define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC OSC_ID_USBSOF
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC32MHZ
#define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_2
#define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1
/*
#define CONFIG_PLL0_SOURCE PLL_SRC_XOSC
#define CONFIG_PLL0_MUL 6
#define CONFIG_PLL0_DIV 1
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL
#define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_2
#define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1
*/
#endif /* CONF_CLOCK_H_INCLUDED */

AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
// ===== System Clock Source Options
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0
// ===== PLL0 Options
//#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0
//#define CONFIG_PLL0_SOURCE PLL_SRC_OSC1
//#define CONFIG_PLL0_MUL 4 /* Fpll = (Fclk * PLL_mul) / PLL_div */
//#define CONFIG_PLL0_DIV 1 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== PLL1 Options
#define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
//#define CONFIG_PLL1_SOURCE PLL_SRC_OSC1
#define CONFIG_PLL1_MUL 8 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define CONFIG_PLL1_DIV 2 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== System Clock Bus Division Options
//#define CONFIG_SYSCLK_CPU_DIV 0 /* Fcpu = Fsys/(2 ^ CPU_div) */
//#define CONFIG_SYSCLK_PBA_DIV 0 /* Fpba = Fsys/(2 ^ PBA_div) */
//#define CONFIG_SYSCLK_PBB_DIV 0 /* Fpbb = Fsys/(2 ^ PBB_div) */
// ===== Peripheral Clock Management Options
//#define CONFIG_SYSCLK_INIT_CPUMASK ((1 << SYSCLK_SYSTIMER) | (1 << SYSCLK_OCD))
//#define CONFIG_SYSCLK_INIT_PBAMASK (1 << SYSCLK_USART0)
//#define CONFIG_SYSCLK_INIT_PBBMASK (1 << SYSCLK_HMATRIX)
//#define CONFIG_SYSCLK_INIT_HSBMASK (1 << SYSCLK_MDMA_HSB)
// ===== USB Clock Source Options
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 1 /* Fusb = Fsys/(2 ^ USB_div) */
#endif /* CONF_CLOCK_H_INCLUDED */

AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
// ===== System Clock Source Options
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0
// ===== PLL0 Options
#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0
//#define CONFIG_PLL0_SOURCE PLL_SRC_OSC1
#define CONFIG_PLL0_MUL 11 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define CONFIG_PLL0_DIV 2 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== PLL1 Options
//#define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
//#define CONFIG_PLL1_SOURCE PLL_SRC_OSC1
//#define CONFIG_PLL1_MUL 8 /* Fpll = (Fclk * PLL_mul) / PLL_div */
//#define CONFIG_PLL1_DIV 2 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== System Clock Bus Division Options
#define CONFIG_SYSCLK_CPU_DIV 0 /* Fcpu = Fsys/(2 ^ CPU_div) */
#define CONFIG_SYSCLK_PBA_DIV 0 /* Fpba = Fsys/(2 ^ PBA_div) */
//#define CONFIG_SYSCLK_PBB_DIV 0 /* Fpbb = Fsys/(2 ^ PBB_div) */
// ===== Peripheral Clock Management Options
//#define CONFIG_SYSCLK_INIT_CPUMASK ((1 << SYSCLK_SYSTIMER) | (1 << SYSCLK_OCD))
//#define CONFIG_SYSCLK_INIT_PBAMASK (1 << SYSCLK_USART0)
//#define CONFIG_SYSCLK_INIT_PBBMASK (1 << SYSCLK_HMATRIX)
//#define CONFIG_SYSCLK_INIT_HSBMASK (1 << SYSCLK_MDMA_HSB)
// ===== USB Clock Source Options
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 1 /* Fusb = Fsys/(2 ^ USB_div) */
#endif /* CONF_CLOCK_H_INCLUDED */

AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
// ===== System Clock Source Options
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC1
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL1
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC8M
// ===== PLL0 Options
#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0
//#define CONFIG_PLL0_SOURCE PLL_SRC_OSC1
//#define CONFIG_PLL0_SOURCE PLL_SRC_RC8M
#define CONFIG_PLL0_MUL 3 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define CONFIG_PLL0_DIV 1 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== PLL1 Options
//#define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
//#define CONFIG_PLL1_SOURCE PLL_SRC_OSC1
//#define CONFIG_PLL1_SOURCE PLL_SRC_RC8M
//#define CONFIG_PLL1_MUL 3 /* Fpll = (Fclk * PLL_mul) / PLL_div */
//#define CONFIG_PLL1_DIV 1 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== System Clock Bus Division Options
//#define CONFIG_SYSCLK_CPU_DIV 0 /* Fcpu = Fsys/(2 ^ CPU_div) */
//#define CONFIG_SYSCLK_PBA_DIV 0 /* Fpba = Fsys/(2 ^ PBA_div) */
//#define CONFIG_SYSCLK_PBB_DIV 0 /* Fpbb = Fsys/(2 ^ PBB_div) */
//#define CONFIG_SYSCLK_PBC_DIV 0 /* Fpbc = Fsys/(2 ^ PBC_div) */
// ===== Peripheral Clock Management Options
//#define CONFIG_SYSCLK_INIT_CPUMASK ((1 << SYSCLK_SYSTIMER) | (1 << SYSCLK_OCD))
//#define CONFIG_SYSCLK_INIT_PBAMASK (1 << SYSCLK_USART0)
//#define CONFIG_SYSCLK_INIT_PBBMASK (1 << SYSCLK_HMATRIX)
//#define CONFIG_SYSCLK_INIT_HSBMASK (1 << SYSCLK_MDMA_HSB)
// ===== USB Clock Source Options
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC1
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 1 /* Fusb = Fsys/(2 ^ USB_div) */
#endif /* CONF_CLOCK_H_INCLUDED */

SAM3S, SAM3SD, SAM4S Devices (UPD: USB Peripheral Device)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
// ===== System Clock (MCK) Source Options
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLBCK
// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
// Use mul and div effective values here.
#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
#define CONFIG_PLL0_MUL 32
#define CONFIG_PLL0_DIV 3
// ===== PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
// Use mul and div effective values here.
#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
#define CONFIG_PLL1_MUL 16
#define CONFIG_PLL1_DIV 2
// ===== USB Clock Source Options (Fusb = FpllX / USB_div)
// Use div effective value here.
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 2
// ===== Target frequency (System clock)
// - XTAL frequency: 12MHz
// - System clock source: PLLA
// - System clock prescaler: 2 (divided by 2)
// - PLLA source: XTAL
// - PLLA output: XTAL * 32 / 3
// - System clock is: 12 * 32 / 3 / 2 = 64MHz
// ===== Target frequency (USB Clock)
// - USB clock source: PLLB
// - USB clock divider: 2 (divided by 2)
// - PLLB output: XTAL * 16 / 2
// - USB clock: 12 * 16 / 2 / 2 = 48MHz
#endif /* CONF_CLOCK_H_INCLUDED */

SAM3U Device (UPDHS: USB Peripheral Device High Speed)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
// ===== System Clock (MCK) Source Options
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK
// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
// Use mul and div effective values here.
#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
#define CONFIG_PLL0_MUL 16
#define CONFIG_PLL0_DIV 1
// ===== UPLL (UTMI) Hardware fixed at 480MHz.
// ===== USB Clock Source fixed at UPLL.
// ===== Target frequency (System clock)
// - XTAL frequency: 12MHz
// - System clock source: PLLA
// - System clock prescaler: 2 (divided by 2)
// - PLLA source: XTAL
// - PLLA output: XTAL * 16 / 1
// - System clock is: 12 * 16 / 1 / 2 = 96MHz
// ===== Target frequency (USB Clock)
// - USB clock source: UPLL
// - UPLL frequency: 480MHz
// - USB clock: 480MHz
#endif /* CONF_CLOCK_H_INCLUDED */

SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
// ===== System Clock (MCK) Source Options
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK
// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES))
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
// Use mul and div effective values here.
#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
#define CONFIG_PLL0_MUL 14
#define CONFIG_PLL0_DIV 1
// ===== UPLL (UTMI) Hardware fixed at 480MHz.
// ===== USB Clock Source Options (Fusb = FpllX / USB_div)
// Use div effective value here.
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL
#define CONFIG_USBCLK_DIV 1
// ===== Target frequency (System clock)
// - XTAL frequency: 12MHz
// - System clock source: PLLA
// - System clock prescaler: 2 (divided by 2)
// - PLLA source: XTAL
// - PLLA output: XTAL * 14 / 1
// - System clock is: 12 * 14 / 1 /2 = 84MHz
// ===== Target frequency (USB Clock)
// - USB clock source: UPLL
// - USB clock divider: 1 (not divided)
// - UPLL frequency: 480MHz
// - USB clock: 480 / 1 = 480MHz
#endif /* CONF_CLOCK_H_INCLUDED */

conf_clocks.h

SAM D21 Device (USB)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false
# define CONF_CLOCK_FLASH_WAIT_STATES 2
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1
# define CONF_CLOCK_OSC8M_ON_DEMAND true
# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE false
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND true
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE false
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE true
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY
# define CONF_CLOCK_DFLL_ON_DEMAND true
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE (512)
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768)
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4)
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4)
/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
# define CONF_CLOCK_DPLL_ENABLE false
# define CONF_CLOCK_DPLL_ON_DEMAND true
# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false
# define CONF_CLOCK_DPLL_LOCK_BYPASS false
# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false
# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1
# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
/* DPLL GCLK reference configuration */
# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE false
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
/* Configure GCLK generator 2 (RTC) */
# define CONF_CLOCK_GCLK_2_ENABLE false
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K
# define CONF_CLOCK_GCLK_2_PRESCALER 32
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
/* Configure GCLK generator 8 */
# define CONF_CLOCK_GCLK_8_ENABLE false
# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_8_PRESCALER 1
# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

conf_board.h

AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
// Only the default board init (switchs/leds) is necessary for this example
#endif /* CONF_BOARD_H_INCLUDED */

AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
// Only the default board init (switchs/leds) is necessary for this example
#endif /* CONF_BOARD_H_INCLUDED */

AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
// Only the default board init (switchs/leds) is necessary for this example
#endif /* CONF_BOARD_H_INCLUDED */

SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
/* Nand flash is used */
#define CONF_BOARD_NAND
// Enable SD MMC interface pins through HSMCI
#define CONF_BOARD_SD_MMC_HSMCI
/* USB pins are used */
#define CONF_BOARD_USB_PORT
#endif /* CONF_BOARD_H_INCLUDED */

SAM D21 Device (USB)

/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
/* Enable USB VBUS detect */
#define CONF_BOARD_USB_VBUS_DETECT
#endif /* CONF_BOARD_H_INCLUDED */
Generated on Fri Mar 4 2022 23:26:32 for SAMD21 by   doxygen 1.8.5