Use a timeout to avoid waiting forever and hanging the system
Global set_clock_divider (volatile avr32_ssc_t *ssc, unsigned int bit_rate, unsigned int pba_hz)
check input values
Global ssc_i2s_init (volatile avr32_ssc_t *ssc, unsigned int sample_frequency, unsigned int data_bit_res, unsigned int frame_bit_res, unsigned char mode, unsigned int pba_hz)
This function assumes that the CPU always runs at the system clock frequency. We want to support at least two more scenarios: Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus clock dividers (which may change at run time). Ditto for all the bus clocks.
This function assumes that the main clock source never changes once it's been set up, and that PLL0 always runs at the compile-time configured default rate. While this is probably the most common configuration, which we want to support as a special case for performance reasons, we will at some point need to support more dynamic setups as well.