Chip-specific PLL definitions.
Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
Data Structures | |
struct | pll_config |
Hardware-specific representation of PLL configuration. More... | |
Macros | |
#define | PLL_TIMEOUT_MS div_ceil(1000 * (PLL_MAX_STARTUP_CYCLES * 2), OSC_SLOW_MIN_HZ) |
Number of milliseconds to wait for PLL lock. More... | |
Chip-specific PLL characteristics | |
#define | PLL_MAX_STARTUP_CYCLES ((1 << AVR32_PM_PLL0_PLLCOUNT_SIZE) - 1) |
Maximum PLL startup time in number of slow clock cycles. More... | |
#define | NR_PLLS 2 |
Number of on-chip PLLs. More... | |
#define | PLL_MIN_HZ 40000000 |
Minimum frequency that the PLL can generate. More... | |
#define | PLL_MAX_HZ 240000000 |
Maximum frequency that the PLL can generate. More... | |
#define | PLL_NR_OPTIONS AVR32_PM_PLL0_PLLOPT_SIZE |
Number of PLL options. More... | |
Chip-specific PLL options | |
#define | PLL_OPT_VCO_RANGE_LOW 0 |
VCO frequency range is 80-180 MHz (160-240 MHz if unset). More... | |
#define | PLL_OPT_OUTPUT_DIV 1 |
Divide output frequency by two. More... | |
#define | PLL_OPT_WBM_DISABLE 2 |
Disable wide-bandwidth mode. More... | |
#define | PLL_VCO_LOW_THRESHOLD |
The threshold under which to set the PLL_OPT_VCO_RANGE_LOW option. More... | |
Enumerations | |
enum | pll_source { PLL_SRC_OSC0 = 0, PLL_SRC_OSC1 = 1, PLL_NR_SOURCES } |
PLL clock source. More... | |
Functions | |
Interaction with the PLL hardware | |
static void | pll_enable (const struct pll_config *cfg, unsigned int pll_id) |
Activate the configuration cfg and enable PLL pll_id. More... | |
static void | pll_disable (unsigned int pll_id) |
Disable the PLL identified by pll_id. More... | |
static bool | pll_is_locked (unsigned int pll_id) |
Determine whether the PLL is locked or not. More... | |
static void | pll_enable_source (enum pll_source src) |
Enable the source of the pll. More... | |
static void | pll_enable_config_defaults (unsigned int pll_id) |
Enable the pll with the default configuration. More... | |
PLL configuration | |
#define | pll_get_default_rate(pll_id) |
Get the default rate in Hz of pll_id. More... | |
#define | pll_config_defaults(cfg, pll_id) |
Initialize PLL configuration using default parameters. More... | |
static void | pll_config_set_option (struct pll_config *cfg, unsigned int option) |
Set the PLL option bit option in the configuration cfg. More... | |
static void | pll_config_clear_option (struct pll_config *cfg, unsigned int option) |
Clear the PLL option bit option in the configuration cfg. More... | |
static void | pll_config_init (struct pll_config *cfg, enum pll_source src, unsigned int div, unsigned int mul) |
The PLL options PLL_OPT_VCO_RANGE_LOW and PLL_OPT_OUTPUT_DIV will be set automatically based on the calculated target frequency. More... | |
static void | pll_config_read (struct pll_config *cfg, unsigned int pll_id) |
Read the currently active configuration of pll_id. More... | |
static void | pll_config_write (const struct pll_config *cfg, unsigned int pll_id) |
Activate the configuration cfg on pll_id. More... | |