mt48lc16m16a2tg7e.h File Reference

Macros
#define	SDRAM_BANK_BITS   2
	The number of bank bits for this SDRAM (1 or 2). More...
#define	SDRAM_CAS   2
	The minimal column address select (READ) latency for this SDRAM (1 to 3 SDRAM cycles). More...
#define	SDRAM_COL_BITS   9
	The number of column bits for this SDRAM (8 to 11). More...
#define	SDRAM_INIT_AUTO_REFRESH_COUNT   2
	The minimal number of AUTO REFRESH commands required during initialization for this SDRAM. More...
#define	SDRAM_ROW_BITS   13
	The number of row bits for this SDRAM (11 to 13). More...
#define	SDRAM_STABLE_CLOCK_INIT_DELAY   100
	The minimal stable-clock initialization delay for this SDRAM. More...
#define	SDRAM_TMRD   2
	The minimal mode register delay time for this SDRAM. More...
#define	SDRAM_TR   7812
	The maximal refresh time for this SDRAM (0 to 4095 SDRAM cycles). More...
#define	SDRAM_TRAS   37
	The minimal row address select time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TRC   60
	The minimal row cycle time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TRCD   15
	The minimal row to column delay time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TRFC   66
	The minimal refresh cycle time for this SDRAM. More...
#define	SDRAM_TRP   15
	The minimal row precharge time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TWR   14
	The minimal write recovery time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TXSR   67
	The minimal exit self refresh time for this SDRAM (0 to 15 SDRAM cycles). More...