at86rf230b.h File Reference

Driver for AT86RF230B transceiver.

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

#include "conf_at86rfx.h"

Macros
#define	AT86RF230   (2)
	Constant RF230 for sub-register SR_PART_NUM. More...
#define	AT86RF230_REV_B   2
	Constant RF230 Rev B for VERSION_NUM. More...
#define	AVREG_1_75V   (1)
#define	AVREG_1_80V   (0)
	Constants for sub-register SR_AVREG_TRIM. More...
#define	AVREG_1_84V   (2)
#define	AVREG_1_88V   (3)
#define	BATMON_ABOVE_THRES   (1)
	Constant BATMON_ABOVE_THRES for sub-register SR_BATMON_OK. More...
#define	BATMON_BELOW_THRES   (0)
	Constant BATMON_BELOW_THRES for sub-register SR_BATMON_OK. More...
#define	BATMON_HIGH_RANGE   (1)
	Constant BATMON_HIGH_RANGE for sub-register BATMON_HR in register RG_BATMON. More...
#define	BATMON_LOW_RANGE   (0)
	Constant BATMON_LOW_RANGE for sub-register BATMON_HR in register RG_BATMON. More...
#define	CCA_DETECTION_TIME_SYM   (8)
#define	CCA_DONE_BIT   (0x80)
#define	CCA_DURATION_SYM   (CCA_DETECTION_TIME_SYM + CCA_PROCESS_TIME_SYM)
#define	CCA_PRE_START_DURATION_US   (20)
#define	CCA_PREPARATION_DURATION_US   (50)
#define	CCA_PROCESS_TIME_SYM   (1)
#define	CCA_STATUS_BIT   (0x40)
#define	CLKM_16MHz   (5)
#define	CLKM_1MHz   (1)
#define	CLKM_2mA   (0)
	Constants for sub-register SR_PAD_IO_CLKM. More...
#define	CLKM_2MHz   (2)
#define	CLKM_4mA   (1)
#define	CLKM_4MHz   (3)
#define	CLKM_6mA   (2)
#define	CLKM_8mA   (3)
#define	CLKM_8MHz   (4)
#define	CLKM_no_clock   (0)
	Constants for sub-register SR_CLKM_CTRL. More...
#define	CRC16_NOT_VALID   (0)
	Constant CRC16_not_valid for sub-register SR_RX_CRC_VALID. More...
#define	CRC16_VALID   (1)
	Constant CRC16_valid for sub-register SR_RX_CRC_VALID. More...
#define	CSMA_PROCESSING_TIME_US   (100)
#define	DVREG_1_75V   (1)
#define	DVREG_1_80V   (0)
	Constants for sub-register SR_DVREG_TRIM. More...
#define	DVREG_1_84V   (2)
#define	DVREG_1_88V   (3)
#define	IRQ_PROCESSING_DLY_US   (32)
#define	P_ON_TO_CLKM_AVAILABLE   (500)
#define	PD_ACK_BIT_SET_DISABLE   (0)
	Constant PD_ACK_BIT_SET_DISABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...
#define	PD_ACK_BIT_SET_ENABLE   (1)
	Constant PD_ACK_BIT_SET_ENABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...
#define	PLL_LOCK_TIME_US   (180) /* us */
#define	PRE_TX_DURATION_US   (32)
#define	RG_BATMON   (0x11)
	Address for register BATMON. More...
#define	RG_CCA_THRES   (0x09)
	Address for register CCA_THRES. More...
#define	RG_CSMA_SEED_0   (0x2d)
	Address for register CSMA_SEED_0. More...
#define	RG_CSMA_SEED_1   (0x2e)
	Address for register CSMA_SEED_1. More...
#define	RG_FTN_CTRL   (0x18)
	Address for register FTN_CTRL. More...
#define	RG_IEEE_ADDR_0   (0x24)
	Address for register IEEE_ADDR_0. More...
#define	RG_IEEE_ADDR_1   (0x25)
	Address for register IEEE_ADDR_1. More...
#define	RG_IEEE_ADDR_2   (0x26)
	Address for register IEEE_ADDR_2. More...
#define	RG_IEEE_ADDR_3   (0x27)
	Address for register IEEE_ADDR_3. More...
#define	RG_IEEE_ADDR_4   (0x28)
	Address for register IEEE_ADDR_4. More...
#define	RG_IEEE_ADDR_5   (0x29)
	Address for register IEEE_ADDR_5. More...
#define	RG_IEEE_ADDR_6   (0x2a)
	Address for register IEEE_ADDR_6. More...
#define	RG_IEEE_ADDR_7   (0x2b)
	Address for register IEEE_ADDR_7. More...
#define	RG_IRQ_MASK   (0x0e)
	Address for register IRQ_MASK. More...
#define	RG_IRQ_STATUS   (0x0f)
	Address for register IRQ_STATUS. More...
#define	RG_MAN_ID_0   (0x1e)
	Address for register MAN_ID_0. More...
#define	RG_MAN_ID_1   (0x1f)
	Address for register MAN_ID_1. More...
#define	RG_PAN_ID_0   (0x22)
	Address for register PAN_ID_0. More...
#define	RG_PAN_ID_1   (0x23)
	Address for register PAN_ID_1. More...
#define	RG_PART_NUM   (0x1c)
	Address for register PART_NUM. More...
#define	RG_PHY_CC_CCA   (0x08)
	Address for register PHY_CC_CCA. More...
#define	RG_PHY_ED_LEVEL   (0x07)
	Address for register PHY_ED_LEVEL. More...
#define	RG_PHY_RSSI   (0x06)
	Address for register PHY_RSSI. More...
#define	RG_PHY_TX_PWR   (0x05)
	Address for register PHY_TX_PWR. More...
#define	RG_PLL_CF   (0x1a)
	Address for register PLL_CF. More...
#define	RG_PLL_DCU   (0x1b)
	Address for register PLL_DCU. More...
#define	RG_SFD_VALUE   (0x0b)
	Offset for register SFD_VALUE. More...
#define	RG_SHORT_ADDR_0   (0x20)
	Address for register SHORT_ADDR_0. More...
#define	RG_SHORT_ADDR_1   (0x21)
	Address for register SHORT_ADDR_1. More...
#define	RG_TRX_CTRL_0   (0x03)
	Address for register TRX_CTRL_0. More...
#define	RG_TRX_STATE   (0x02)
	Constants for sub-register SR_TRX_STATUS. More...
#define	RG_TRX_STATUS   (0x01)
#define	RG_VERSION_NUM   (0x1d)
	Address for register VERSION_NUM. More...
#define	RG_VREG_CTRL   (0x10)
	Address for register VREG_CTRL. More...
#define	RG_XAH_CTRL   (0x2c)
	Address for register XAH_CTRL. More...
#define	RG_XOSC_CTRL   (0x12)
	Address for register XOSC_CTRL. More...
#define	RSSI_BASE_VAL   (-91)
	RSSI Base Value. More...
#define	RST_PULSE_WIDTH_US   (6)
#define	SLEEP_TO_TRX_OFF_US   (880)
#define	SLP_TR_TOGGLE_US   (2)
#define	SR_AACK_SET_PD   0x2e, 0x20, 5
	Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...
#define	SR_AVDD_OK   0x10, 0x40, 6
	Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL. More...
#define	SR_AVREG_EXT   0x10, 0x80, 7
	Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL. More...
#define	SR_AVREG_TRIM   0x10, 0x30, 4
	Access parameters for sub-register AVREG_TRIM in register RG_VREG_CTRL. More...
#define	SR_BATMON_HR   0x11, 0x10, 4
#define	SR_BATMON_OK   0x11, 0x20, 5
	Access parameters for sub-registers in register RG_BATMON. More...
#define	SR_BATMON_VTH   0x11, 0x0f, 0
#define	SR_CCA_CS_THRES   0x09, 0xf0, 4
	Access parameters for sub-registers in register RG_CCA_THRES. More...
#define	SR_CCA_DONE   0x01, 0x80, 7
	Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS. More...
#define	SR_CCA_ED_THRES   0x09, 0x0f, 0
#define	SR_CCA_MODE   0x08, 0x60, 5
#define	SR_CCA_REQUEST   0x08, 0x80, 7
	Access parameters for sub-registers in register RG_PHY_CC_CCA. More...
#define	SR_CCA_STATUS   0x01, 0x40, 6
	Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS. More...
#define	SR_CHANNEL   0x08, 0x1f, 0
#define	SR_CLKM_CTRL   0x03, 0x07, 0
	Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0. More...
#define	SR_CLKM_SHA_SEL   0x03, 0x08, 3
	Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0. More...
#define	SR_CSMA_SEED_0   0x2d, 0xff, 0
	Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0. More...
#define	SR_CSMA_SEED_1   0x2e, 0x07, 0
	Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1. More...
#define	SR_DVDD_OK   0x10, 0x04, 2
#define	SR_DVREG_EXT   0x10, 0x08, 3
	Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL. More...
#define	SR_DVREG_TRIM   0x10, 0x03, 0
#define	SR_ED_LEVEL   0x07, 0xff, 0
	Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL. More...
#define	SR_FTN_START   0x18, 0x80, 7
	Access parameters for sub-register FTN_START in register RG_FTN_CTRL. More...
#define	SR_FTNV   0x18, 0x3f, 0
	Access parameters for sub-register FTNV in register RG_FTN_CTRL. More...
#define	SR_I_AM_COORD   0x2e, 0x08, 3
	Access parameters for sub-register I_AM_COORD in register RG_CSMA_SEED_1. More...
#define	SR_IEEE_ADDR_0   0x24, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0. More...
#define	SR_IEEE_ADDR_1   0x25, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1. More...
#define	SR_IEEE_ADDR_2   0x26, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2. More...
#define	SR_IEEE_ADDR_3   0x27, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3. More...
#define	SR_IEEE_ADDR_4   0x28, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4. More...
#define	SR_IEEE_ADDR_5   0x29, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5. More...
#define	SR_IEEE_ADDR_6   0x2a, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6. More...
#define	SR_IEEE_ADDR_7   0x2b, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7. More...
#define	SR_IRQ_0_PLL_LOCK   0x0f, 0x01, 0
#define	SR_IRQ_1_PLL_UNLOCK   0x0f, 0x02, 1
#define	SR_IRQ_2_RX_START   0x0f, 0x04, 2
#define	SR_IRQ_3_TRX_END   0x0f, 0x08, 3
#define	SR_IRQ_4   0x0f, 0x10, 4
#define	SR_IRQ_5   0x0f, 0x20, 5
#define	SR_IRQ_6_TRX_UR   0x0f, 0x40, 6
#define	SR_IRQ_7_BAT_LOW   0x0f, 0x80, 7
	Access parameters for sub-registers in register RG_IRQ_STATUS. More...
#define	SR_IRQ_MASK   0x0e, 0xff, 0
	Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK. More...
#define	SR_MAN_ID_0   0x1e, 0xff, 0
	Access parameters for sub-registers in register RG_MAN_ID_0. More...
#define	SR_MAN_ID_1   0x1f, 0xff, 0
	Access parameters for sub-registers in register RG_MAN_ID_1. More...
#define	SR_MAX_CSMA_RETRIES   0x2c, 0x0e, 1
	Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL. More...
#define	SR_MAX_FRAME_RETRIES   0x2c, 0xf0, 4
	Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL. More...
#define	SR_MIN_BE   0x2e, 0xc0, 6
	Access parameters for sub-register MIN_BE in register RG_CSMA_SEED_1. More...
#define	SR_PAD_IO   0x03, 0xc0, 6
	Access parameters for sub-registers in register RG_TRX_CTRL_0. More...
#define	SR_PAD_IO_CLKM   0x03, 0x30, 4
	Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0. More...
#define	SR_PAN_ID_0   0x22, 0xff, 0
	Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0. More...
#define	SR_PAN_ID_1   0x23, 0xff, 0
	Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1. More...
#define	SR_PART_NUM   0x1c, 0xff, 0
	Access parameters for sub-register PART_NUM in register RG_PART_NUM. More...
#define	SR_PLL_CF   0x1a, 0x0f, 0
	Access parameters for sub-register PLL_CF in register RG_PLL_CF. More...
#define	SR_PLL_CF_START   0x1a, 0x80, 7
	Access parameters for sub-register PLL_CF_START in register RG_PLL_CF. More...
#define	SR_PLL_DCU_START   0x1b, 0x80, 7
	Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU. More...
#define	SR_PLL_DCUW   0x1b, 0x3f, 0
	Access parameters for sub-register PLL_DCUW in register RG_PLL_DCU. More...
#define	SR_reserved_01_3   0x01, 0x20, 5
#define	SR_reserved_05_2   0x05, 0x70, 4
#define	SR_reserved_06_2   0x06, 0x60, 5
#define	SR_reserved_11_1   0x11, 0xc0, 6
#define	SR_reserved_18_2   0x18, 0x40, 6
#define	SR_reserved_1a_2   0x1a, 0x70, 4
#define	SR_reserved_1b_2   0x1b, 0x40, 6
#define	SR_reserved_2c_3   0x2c, 0x01, 0
#define	SR_reserved_2e_3   0x2e, 0x10, 4
#define	SR_RSSI   0x06, 0x1f, 0
	Access parameters for sub-register RSSI in register RG_PHY_RSSI. More...
#define	SR_RX_CRC_VALID   0x06, 0x80, 7
	Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI. More...
#define	SR_SHORT_ADDR_0   0x20, 0xff, 0
	Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0. More...
#define	SR_SHORT_ADDR_1   0x21, 0xff, 0
	Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1. More...
#define	SR_TRAC_STATUS   0x02, 0xe0, 5
	Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE. More...
#define	SR_TRX_CMD   0x02, 0x1f, 0
	Access parameters for sub-register TRX_CMD in register RG_TRX_STATE. More...
#define	SR_TRX_STATUS   0x01, 0x1f, 0
	Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS. More...
#define	SR_TX_AUTO_CRC_ON   0x05, 0x80, 7
#define	SR_TX_PWR   0x05, 0x0f, 0
	Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR. More...
#define	SR_VERSION_NUM   0x1d, 0xff, 0
	Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM. More...
#define	SR_XTAL_MODE   0x12, 0xf0, 4
	Access parameters for sub-registers in register RG_XOSC_CTRL. More...
#define	SR_XTAL_TRIM   0x12, 0x0f, 0
#define	TRAC_CHANNEL_ACCESS_FAILURE   (3)
#define	TRAC_INVALID   (7)
#define	TRAC_NO_ACK   (5)
#define	TRAC_SUCCESS   (0)
	Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS. More...
#define	TRAC_SUCCESS_DATA_PENDING   (1)
#define	TRX_OFF_TO_SLEEP_TIME   (35) /* us */
#define	TRX_SUPPORTED_CHANNELS   (0x07FFF800)
#define	TX_AUTO_CRC_DISABLE   (0)
	Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON. More...
#define	TX_AUTO_CRC_ENABLE   (1)
	Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON. More...
#define	TX_AUTO_CRC_ON   0x80
	Access parameters for sub-register TX_AUTO_CRC_ON in register RG_PHY_TX_PWR. More...
#define	TX_PWR_TOLERANCE   (0x80)
	Tolerance of the phyTransmitPower PIB attribute. More...

Typedefs
typedef enum sleep_mode_tag	sleep_mode_t
	Sleep Mode supported by transceiver. More...
typedef enum tal_state_tag	tal_state_t
	TAL states. More...
typedef enum tal_trx_status_tag	tal_trx_status_t
	Transceiver states. More...
typedef enum tal_tx_sub_state_tag	tal_tx_sub_state_t
typedef enum trx_cmd_tag	trx_cmd_t
	Transceiver commands. More...
typedef enum trx_irq_reason_tag	trx_irq_reason_t
	Transceiver interrupt reasons. More...
typedef enum trx_retval_tag	trx_retval_t
	These are the return values of the AT86RF230B APIs. More...

Enumerations
enum	sleep_mode_tag { SLEEP_MODE_1 }
	Sleep Mode supported by transceiver. More...
enum	tal_state_tag {   TAL_IDLE = 0,   TAL_TX_AUTO = 1,   TAL_TX_END = 2 }
	TAL states. More...
enum	tal_trx_status_tag {   P_ON = 0,   BUSY_RX = 1,   BUSY_TX = 2,   RX_ON = 6,   TRX_OFF = 8,   PLL_ON = 9,   TRX_SLEEP = 15,   BUSY_RX_AACK = 17,   BUSY_TX_ARET = 18,   RX_AACK_ON = 22,   TX_ARET_ON = 25,   RX_ON_NOCLK = 28,   RX_AACK_ON_NOCLK = 29,   BUSY_RX_AACK_NOCLK = 30,   STATE_TRANSITION_IN_PROGRESS = 31 }
	Transceiver states. More...
enum	tal_tx_sub_state_tag {   TAL_TX_FRAME_PENDING = (1 << 4),   TAL_TX_SUCCESS = (2 << 4),   TAL_TX_ACCESS_FAILURE = (3 << 4),   TAL_TX_NO_ACK = (4 << 4),   TAL_TX_FAILURE = (5 << 4),   TAL_TX_ACK_REQUIRED = (6 << 4) }
enum	trx_cmd_tag {   CMD_NOP = (0),   CMD_TX_START = (2),   CMD_FORCE_TRX_OFF = (3),   CMD_RX_ON = (6),   CMD_TRX_OFF = (8),   CMD_PLL_ON = (9),   CMD_FORCE_PLL_ON = (10),   CMD_RX_AACK_ON = (22),   CMD_TX_ARET_ON = (25),   CMD_TRX_SLEEP = (26) }
	Transceiver commands. More...
enum	trx_irq_reason_tag {   TRX_NO_IRQ = (0x00),   TRX_IRQ_4 = (0x10),   TRX_IRQ_5 = (0x20),   TRX_IRQ_BAT_LOW = (0x80),   TRX_IRQ_PLL_LOCK = (0x01),   TRX_IRQ_PLL_UNLOCK = (0x02),   TRX_IRQ_RX_START = (0x04),   TRX_IRQ_TRX_END = (0x08),   TRX_IRQ_TRX_UR = (0x40) }
	Transceiver interrupt reasons. More...
enum	trx_retval_tag {   TRX_SUCCESS = 0x00,   TRX_FAILURE = 0x01,   TRX_CHANNEL_ACCESS_FAILURE = 0x02 }
	These are the return values of the AT86RF230B APIs. More...

Functions
void	handle_tal_state (void)
	Handles the transceiver state. More...
trx_retval_t	tal_init (void)
	Initializes the TAL. More...
void	trx_irq_handler_cb (void)
	Transceiver interrupt handler. More...
void	tx_frame_config (void)
	Configures the transceiver for frame transmission. More...

Variables
bool	at86rfx_frame_rx

#define AT86RF230   (2)

Constant RF230 for sub-register SR_PART_NUM.

Referenced by trx_init().

#define AT86RF230_REV_B   2

Constant RF230 Rev B for VERSION_NUM.

Referenced by trx_init().

#define AVREG_1_75V   (1)

#define AVREG_1_80V   (0)

Constants for sub-register SR_AVREG_TRIM.

#define AVREG_1_84V   (2)

#define AVREG_1_88V   (3)

#define BATMON_ABOVE_THRES   (1)

Constant BATMON_ABOVE_THRES for sub-register SR_BATMON_OK.

#define BATMON_BELOW_THRES   (0)

Constant BATMON_BELOW_THRES for sub-register SR_BATMON_OK.

#define BATMON_HIGH_RANGE   (1)

Constant BATMON_HIGH_RANGE for sub-register BATMON_HR in register RG_BATMON.

#define BATMON_LOW_RANGE   (0)

Constant BATMON_LOW_RANGE for sub-register BATMON_HR in register RG_BATMON.

#define CCA_DETECTION_TIME_SYM   (8)

#define CCA_DONE_BIT   (0x80)

#define CCA_DURATION_SYM   (CCA_DETECTION_TIME_SYM + CCA_PROCESS_TIME_SYM)

#define CCA_PRE_START_DURATION_US   (20)

#define CCA_PREPARATION_DURATION_US   (50)

#define CCA_PROCESS_TIME_SYM   (1)

#define CCA_STATUS_BIT   (0x40)

#define CLKM_16MHz   (5)

#define CLKM_1MHz   (1)

Referenced by trx_config().

#define CLKM_2mA   (0)

Constants for sub-register SR_PAD_IO_CLKM.

Referenced by trx_config().

#define CLKM_2MHz   (2)

#define CLKM_4mA   (1)

#define CLKM_4MHz   (3)

#define CLKM_6mA   (2)

#define CLKM_8mA   (3)

#define CLKM_8MHz   (4)

#define CLKM_no_clock   (0)

Constants for sub-register SR_CLKM_CTRL.

#define CRC16_NOT_VALID   (0)

Constant CRC16_not_valid for sub-register SR_RX_CRC_VALID.

Referenced by handle_received_frame_irq().

#define CRC16_VALID   (1)

Constant CRC16_valid for sub-register SR_RX_CRC_VALID.

#define CSMA_PROCESSING_TIME_US   (100)

#define DVREG_1_75V   (1)

#define DVREG_1_80V   (0)

Constants for sub-register SR_DVREG_TRIM.

#define DVREG_1_84V   (2)

#define DVREG_1_88V   (3)

#define IRQ_PROCESSING_DLY_US   (32)

#define P_ON_TO_CLKM_AVAILABLE   (500)

Referenced by trx_init().

#define PD_ACK_BIT_SET_DISABLE   (0)

Constant PD_ACK_BIT_SET_DISABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

#define PD_ACK_BIT_SET_ENABLE   (1)

Constant PD_ACK_BIT_SET_ENABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

Referenced by trx_config().

#define PLL_LOCK_TIME_US   (180) /* us */

#define PRE_TX_DURATION_US   (32)

#define RG_BATMON   (0x11)

Address for register BATMON.

#define RG_CCA_THRES   (0x09)

Address for register CCA_THRES.

#define RG_CSMA_SEED_0   (0x2d)

Address for register CSMA_SEED_0.

Referenced by trx_config().

#define RG_CSMA_SEED_1   (0x2e)

Address for register CSMA_SEED_1.

#define RG_FTN_CTRL   (0x18)

Address for register FTN_CTRL.

#define RG_IEEE_ADDR_0   (0x24)

Address for register IEEE_ADDR_0.

#define RG_IEEE_ADDR_1   (0x25)

Address for register IEEE_ADDR_1.

#define RG_IEEE_ADDR_2   (0x26)

Address for register IEEE_ADDR_2.

#define RG_IEEE_ADDR_3   (0x27)

Address for register IEEE_ADDR_3.

#define RG_IEEE_ADDR_4   (0x28)

Address for register IEEE_ADDR_4.

#define RG_IEEE_ADDR_5   (0x29)

Address for register IEEE_ADDR_5.

#define RG_IEEE_ADDR_6   (0x2a)

Address for register IEEE_ADDR_6.

#define RG_IEEE_ADDR_7   (0x2b)

Address for register IEEE_ADDR_7.

#define RG_IRQ_MASK   (0x0e)

Address for register IRQ_MASK.

Referenced by switch_pll_on(), and trx_config().

#define RG_IRQ_STATUS   (0x0f)

Address for register IRQ_STATUS.

Referenced by switch_pll_on(), tal_init(), and trx_irq_handler_cb().

#define RG_MAN_ID_0   (0x1e)

Address for register MAN_ID_0.

#define RG_MAN_ID_1   (0x1f)

Address for register MAN_ID_1.

#define RG_PAN_ID_0   (0x22)

Address for register PAN_ID_0.

#define RG_PAN_ID_1   (0x23)

Address for register PAN_ID_1.

#define RG_PART_NUM   (0x1c)

Address for register PART_NUM.

Referenced by trx_init().

#define RG_PHY_CC_CCA   (0x08)

Address for register PHY_CC_CCA.

#define RG_PHY_ED_LEVEL   (0x07)

Address for register PHY_ED_LEVEL.

#define RG_PHY_RSSI   (0x06)

Address for register PHY_RSSI.

#define RG_PHY_TX_PWR   (0x05)

Address for register PHY_TX_PWR.

#define RG_PLL_CF   (0x1a)

Address for register PLL_CF.

#define RG_PLL_DCU   (0x1b)

Address for register PLL_DCU.

#define RG_SFD_VALUE   (0x0b)

Offset for register SFD_VALUE.

#define RG_SHORT_ADDR_0   (0x20)

Address for register SHORT_ADDR_0.

#define RG_SHORT_ADDR_1   (0x21)

Address for register SHORT_ADDR_1.

#define RG_TRX_CTRL_0   (0x03)

Address for register TRX_CTRL_0.

Referenced by trx_config().

#define RG_TRX_STATE   (0x02)

Constants for sub-register SR_TRX_STATUS.

Address for register TRX_STATE

Referenced by at86rfx_init(), set_trx_state(), switch_pll_on(), and trx_init().

#define RG_TRX_STATUS   (0x01)

#define RG_VERSION_NUM   (0x1d)

Address for register VERSION_NUM.

Referenced by trx_init().

#define RG_VREG_CTRL   (0x10)

Address for register VREG_CTRL.

#define RG_XAH_CTRL   (0x2c)

Address for register XAH_CTRL.

#define RG_XOSC_CTRL   (0x12)

Address for register XOSC_CTRL.

#define RSSI_BASE_VAL   (-91)

RSSI Base Value.

#define RST_PULSE_WIDTH_US   (6)

Referenced by trx_init(), and trx_reset().

#define SLEEP_TO_TRX_OFF_US   (880)

Referenced by trx_reset().

#define SLP_TR_TOGGLE_US   (2)

#define SR_AACK_SET_PD   0x2e, 0x20, 5

Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

Referenced by trx_config().

#define SR_AVDD_OK   0x10, 0x40, 6

Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL.

#define SR_AVREG_EXT   0x10, 0x80, 7

Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL.

#define SR_AVREG_TRIM   0x10, 0x30, 4

Access parameters for sub-register AVREG_TRIM in register RG_VREG_CTRL.

#define SR_BATMON_HR   0x11, 0x10, 4

#define SR_BATMON_OK   0x11, 0x20, 5

Access parameters for sub-registers in register RG_BATMON.

#define SR_BATMON_VTH   0x11, 0x0f, 0

#define SR_CCA_CS_THRES   0x09, 0xf0, 4

Access parameters for sub-registers in register RG_CCA_THRES.

#define SR_CCA_DONE   0x01, 0x80, 7

Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS.

#define SR_CCA_ED_THRES   0x09, 0x0f, 0

#define SR_CCA_MODE   0x08, 0x60, 5

Referenced by tal_init().

#define SR_CCA_REQUEST   0x08, 0x80, 7

Access parameters for sub-registers in register RG_PHY_CC_CCA.

#define SR_CCA_STATUS   0x01, 0x40, 6

Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS.

#define SR_CHANNEL   0x08, 0x1f, 0

Referenced by at86rfx_init().

#define SR_CLKM_CTRL   0x03, 0x07, 0

Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0.

#define SR_CLKM_SHA_SEL   0x03, 0x08, 3

Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0.

#define SR_CSMA_SEED_0   0x2d, 0xff, 0

Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0.

#define SR_CSMA_SEED_1   0x2e, 0x07, 0

Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1.

Referenced by trx_config().

#define SR_DVDD_OK   0x10, 0x04, 2

#define SR_DVREG_EXT   0x10, 0x08, 3

Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL.

#define SR_DVREG_TRIM   0x10, 0x03, 0

#define SR_ED_LEVEL   0x07, 0xff, 0

Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL.

#define SR_FTN_START   0x18, 0x80, 7

Access parameters for sub-register FTN_START in register RG_FTN_CTRL.

#define SR_FTNV   0x18, 0x3f, 0

Access parameters for sub-register FTNV in register RG_FTN_CTRL.

#define SR_I_AM_COORD   0x2e, 0x08, 3

Access parameters for sub-register I_AM_COORD in register RG_CSMA_SEED_1.

#define SR_IEEE_ADDR_0   0x24, 0xff, 0

Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0.

#define SR_IEEE_ADDR_1   0x25, 0xff, 0

Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1.

#define SR_IEEE_ADDR_2   0x26, 0xff, 0

Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2.

#define SR_IEEE_ADDR_3   0x27, 0xff, 0

Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3.

#define SR_IEEE_ADDR_4   0x28, 0xff, 0

Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4.

#define SR_IEEE_ADDR_5   0x29, 0xff, 0

Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5.

#define SR_IEEE_ADDR_6   0x2a, 0xff, 0

Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6.

#define SR_IEEE_ADDR_7   0x2b, 0xff, 0

Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7.

#define SR_IRQ_0_PLL_LOCK   0x0f, 0x01, 0

#define SR_IRQ_1_PLL_UNLOCK   0x0f, 0x02, 1

#define SR_IRQ_2_RX_START   0x0f, 0x04, 2

#define SR_IRQ_3_TRX_END   0x0f, 0x08, 3

#define SR_IRQ_4   0x0f, 0x10, 4

#define SR_IRQ_5   0x0f, 0x20, 5

#define SR_IRQ_6_TRX_UR   0x0f, 0x40, 6

#define SR_IRQ_7_BAT_LOW   0x0f, 0x80, 7

Access parameters for sub-registers in register RG_IRQ_STATUS.

#define SR_IRQ_MASK   0x0e, 0xff, 0

Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK.

#define SR_MAN_ID_0   0x1e, 0xff, 0

Access parameters for sub-registers in register RG_MAN_ID_0.

#define SR_MAN_ID_1   0x1f, 0xff, 0

Access parameters for sub-registers in register RG_MAN_ID_1.

#define SR_MAX_CSMA_RETRIES   0x2c, 0x0e, 1

Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL.

#define SR_MAX_FRAME_RETRIES   0x2c, 0xf0, 4

Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL.

#define SR_MIN_BE   0x2e, 0xc0, 6

Access parameters for sub-register MIN_BE in register RG_CSMA_SEED_1.

Referenced by tal_init().

#define SR_PAD_IO   0x03, 0xc0, 6

Access parameters for sub-registers in register RG_TRX_CTRL_0.

#define SR_PAD_IO_CLKM   0x03, 0x30, 4

Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0.

#define SR_PAN_ID_0   0x22, 0xff, 0

Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0.

#define SR_PAN_ID_1   0x23, 0xff, 0

Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1.

#define SR_PART_NUM   0x1c, 0xff, 0

Access parameters for sub-register PART_NUM in register RG_PART_NUM.

#define SR_PLL_CF   0x1a, 0x0f, 0

Access parameters for sub-register PLL_CF in register RG_PLL_CF.

#define SR_PLL_CF_START   0x1a, 0x80, 7

Access parameters for sub-register PLL_CF_START in register RG_PLL_CF.

#define SR_PLL_DCU_START   0x1b, 0x80, 7

Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU.

#define SR_PLL_DCUW   0x1b, 0x3f, 0

Access parameters for sub-register PLL_DCUW in register RG_PLL_DCU.

#define SR_reserved_01_3   0x01, 0x20, 5

#define SR_reserved_05_2   0x05, 0x70, 4

#define SR_reserved_06_2   0x06, 0x60, 5

#define SR_reserved_11_1   0x11, 0xc0, 6

#define SR_reserved_18_2   0x18, 0x40, 6

#define SR_reserved_1a_2   0x1a, 0x70, 4

#define SR_reserved_1b_2   0x1b, 0x40, 6

#define SR_reserved_2c_3   0x2c, 0x01, 0

#define SR_reserved_2e_3   0x2e, 0x10, 4

#define SR_RSSI   0x06, 0x1f, 0

Access parameters for sub-register RSSI in register RG_PHY_RSSI.

#define SR_RX_CRC_VALID   0x06, 0x80, 7

Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI.

Referenced by handle_received_frame_irq().

#define SR_SHORT_ADDR_0   0x20, 0xff, 0

Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0.

#define SR_SHORT_ADDR_1   0x21, 0xff, 0

Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1.

#define SR_TRAC_STATUS   0x02, 0xe0, 5

Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE.

#define SR_TRX_CMD   0x02, 0x1f, 0

Access parameters for sub-register TRX_CMD in register RG_TRX_STATE.

#define SR_TRX_STATUS   0x01, 0x1f, 0

Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS.

Referenced by set_trx_state(), switch_pll_on(), trx_init(), and trx_reset().

#define SR_TX_AUTO_CRC_ON   0x05, 0x80, 7

Referenced by trx_config().

#define SR_TX_PWR   0x05, 0x0f, 0

Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR.

#define SR_VERSION_NUM   0x1d, 0xff, 0

Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM.

#define SR_XTAL_MODE   0x12, 0xf0, 4

Access parameters for sub-registers in register RG_XOSC_CTRL.

#define SR_XTAL_TRIM   0x12, 0x0f, 0

#define TRAC_CHANNEL_ACCESS_FAILURE   (3)

Referenced by tx_end_handling().

#define TRAC_INVALID   (7)

Referenced by tx_end_handling().

#define TRAC_NO_ACK   (5)

#define TRAC_SUCCESS   (0)

Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.

Referenced by tx_end_handling().

#define TRAC_SUCCESS_DATA_PENDING   (1)

#define TRX_OFF_TO_SLEEP_TIME   (35) /* us */

#define TRX_SUPPORTED_CHANNELS   (0x07FFF800)

#define TX_AUTO_CRC_DISABLE   (0)

Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON.

#define TX_AUTO_CRC_ENABLE   (1)

Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON.

Referenced by trx_config().

#define TX_AUTO_CRC_ON   0x80

Access parameters for sub-register TX_AUTO_CRC_ON in register RG_PHY_TX_PWR.

#define TX_PWR_TOLERANCE   (0x80)

Tolerance of the phyTransmitPower PIB attribute.

This is encoded into the two MSBits of the attribute, and is effectively read-only.

typedef enum sleep_mode_tag sleep_mode_t

Sleep Mode supported by transceiver.

typedef enum tal_state_tag tal_state_t

TAL states.

typedef enum tal_trx_status_tag tal_trx_status_t

Transceiver states.

typedef enum tal_tx_sub_state_tag tal_tx_sub_state_t

typedef enum trx_cmd_tag trx_cmd_t

Transceiver commands.

typedef enum trx_irq_reason_tag trx_irq_reason_t

Transceiver interrupt reasons.

typedef enum trx_retval_tag trx_retval_t

These are the return values of the AT86RF230B APIs.

enum sleep_mode_tag

Sleep Mode supported by transceiver.

Enumerator
SLEEP_MODE_1

enum tal_state_tag

TAL states.

Enumerator
TAL_IDLE
TAL_TX_AUTO
TAL_TX_END

enum tal_trx_status_tag

Transceiver states.

Enumerator
P_ON
BUSY_RX
BUSY_TX
RX_ON
TRX_OFF
PLL_ON
TRX_SLEEP
BUSY_RX_AACK
BUSY_TX_ARET
RX_AACK_ON
TX_ARET_ON
RX_ON_NOCLK
RX_AACK_ON_NOCLK
BUSY_RX_AACK_NOCLK
STATE_TRANSITION_IN_PROGRESS

enum tal_tx_sub_state_tag

Enumerator
TAL_TX_FRAME_PENDING
TAL_TX_SUCCESS
TAL_TX_ACCESS_FAILURE
TAL_TX_NO_ACK
TAL_TX_FAILURE
TAL_TX_ACK_REQUIRED

enum trx_cmd_tag

Transceiver commands.

Enumerator
CMD_NOP
CMD_TX_START
CMD_FORCE_TRX_OFF
CMD_RX_ON
CMD_TRX_OFF
CMD_PLL_ON
CMD_FORCE_PLL_ON
CMD_RX_AACK_ON
CMD_TX_ARET_ON
CMD_TRX_SLEEP

enum trx_irq_reason_tag

Transceiver interrupt reasons.

Enumerator
TRX_NO_IRQ
TRX_IRQ_4
TRX_IRQ_5
TRX_IRQ_BAT_LOW
TRX_IRQ_PLL_LOCK
TRX_IRQ_PLL_UNLOCK
TRX_IRQ_RX_START
TRX_IRQ_TRX_END
TRX_IRQ_TRX_UR

enum trx_retval_tag

These are the return values of the AT86RF230B APIs.

Enumerator
TRX_SUCCESS
TRX_FAILURE
TRX_CHANNEL_ACCESS_FAILURE

bool at86rfx_frame_rx

Referenced by at86rfx_task(), and handle_received_frame_irq().