The DMA (Direct Memory Access Controller) Controller transfers data from a source peripheral to a destination peripheral over one or more System Bus.
Data Structures | |
struct | dmaca_channel_options_t |
struct | dmaca_interrupt_t |
Macros | |
#define | BYTE AVR32_DMACA_8_BITS |
Transfer width. More... | |
#define | CHUNK_1 AVR32_DMACA_1_DATA_ITEM |
Chunk size. More... | |
#define | CHUNK_16 AVR32_DMACA_16_DATA_ITEMS |
#define | CHUNK_32 AVR32_DMACA_32_DATA_ITEMS |
#define | CHUNK_4 AVR32_DMACA_4_DATA_ITEMS |
#define | CHUNK_8 AVR32_DMACA_8_DATA_ITEMS |
#define | DEC_MODE AVR32_DMACA_DECREMENT |
#define | DMACA1 0 |
HSB interfaces. More... | |
#define | DMACA2 1 |
#define | DMACA_M2M AVR32_DMACA_MEM_TO_MEM_BY_DMACA |
Flow controller mode. More... | |
#define | DMACA_M2P AVR32_DMACA_MEM_TO_PRPH_BY_DMACA |
#define | DMACA_P2M AVR32_DMACA_PRPH_TO_MEM_BY_DMACA |
#define | DMACA_P2P AVR32_DMACA_PRPH_TO_PRPH_BY_DMACA |
#define | DW_DMAC_CHAN_CFG 0x040 |
#define | DW_DMAC_CHAN_CTL 0x018 |
#define | DW_DMAC_CHAN_DAR 0x008 |
#define | DW_DMAC_CHAN_LLP 0x010 |
#define | DW_DMAC_CHAN_SAR 0x000 |
#define | false 0 |
General. More... | |
#define | FIX_MODE AVR32_DMACA_NO_CHANGE |
#define | HALF_WORD AVR32_DMACA_16_BITS |
#define | HARDWARE AVR32_DMACA_HARDWARE |
#define | HIF0 0 |
Handshake interfaces. More... | |
#define | HIF1 1 |
#define | HIF2 2 |
#define | HIF3 3 |
#define | HIF4 4 |
#define | HIF5 5 |
#define | INC_MODE AVR32_DMACA_INCREMENT |
#define | SOFTWARE AVR32_DMACA_SOFTWARE |
Hardware/Software Handshaking select. More... | |
#define | true 1 |
#define | WORD AVR32_DMACA_32_BITS |
#define BYTE AVR32_DMACA_8_BITS |
Transfer width.
#define CHUNK_1 AVR32_DMACA_1_DATA_ITEM |
Chunk size.
#define CHUNK_16 AVR32_DMACA_16_DATA_ITEMS |
#define CHUNK_32 AVR32_DMACA_32_DATA_ITEMS |
#define CHUNK_4 AVR32_DMACA_4_DATA_ITEMS |
#define CHUNK_8 AVR32_DMACA_8_DATA_ITEMS |
#define DEC_MODE AVR32_DMACA_DECREMENT |
#define DMACA1 0 |
HSB interfaces.
#define DMACA2 1 |
#define DMACA_M2M AVR32_DMACA_MEM_TO_MEM_BY_DMACA |
Flow controller mode.
#define DMACA_M2P AVR32_DMACA_MEM_TO_PRPH_BY_DMACA |
#define DMACA_P2M AVR32_DMACA_PRPH_TO_MEM_BY_DMACA |
#define DMACA_P2P AVR32_DMACA_PRPH_TO_PRPH_BY_DMACA |
#define DW_DMAC_CHAN_CFG 0x040 |
#define DW_DMAC_CHAN_CTL 0x018 |
#define DW_DMAC_CHAN_DAR 0x008 |
#define DW_DMAC_CHAN_LLP 0x010 |
#define DW_DMAC_CHAN_SAR 0x000 |
#define false 0 |
General.
#define FIX_MODE AVR32_DMACA_NO_CHANGE |
#define HALF_WORD AVR32_DMACA_16_BITS |
#define HARDWARE AVR32_DMACA_HARDWARE |
#define HIF0 0 |
Handshake interfaces.
#define HIF1 1 |
#define HIF2 2 |
#define HIF3 3 |
#define HIF4 4 |
#define HIF5 5 |
#define INC_MODE AVR32_DMACA_INCREMENT |
#define SOFTWARE AVR32_DMACA_SOFTWARE |
Hardware/Software Handshaking select.
#define true 1 |
#define WORD AVR32_DMACA_32_BITS |