This is the documentation for the data structures, functions, variables, defines, enums, and typedefs for the power manager driver.
It also gives an example of the usage of the PM on UC3 products. This example shows how to configure the Power Manager(PM) and the System Control Interface(SCIF) (only for devices that include a SCIF module) to use Oscillator 0 as source of main clock and configure a generic clock GCLK with this OSC0 as input. The generic clock 0 can be then viewed on the GCLK pin (this is the oscillator 0 frequency). Once these configurations are done, the example goes into sleep mode while still maintaining GCLK output.
This software was written for the GNU GCC for AVR32 and IAR Systems compiler for AVR32. Other compilers may or may not work.
All AVR32 devices with a PM module or AVR32 devices with a PM module and a SCIF module can be used. This example has been tested with the following setup:
CPU speed: OSC0 MHz
On EVK1100, GCLK_0_1 is pin number 51 (PB19) with AT32UC3A0512 in QFP144 package.
On EVK1101, GCLK_2 is pin number 30 (PA30) with AT32UCB0256 in QFP64 package.
On EVK1104, GCLK_1_0 is pin number 43 (PB11) with AT32UC3A3256 in QFP144 package.
On the STK600 + RCUC3L0 setup, insert a 12MHz crystal in the STK600 crystal socket. GCLK_1_0 is GPIO pin 6/pin pa06/pin#10 on a UC3L QFP48 package; for the RCUC3L0 routing card, this pin is mapped on STK600.PORTA.PA6.
On the STK600 + RCUC3D setup, insert a 12MHz crystal in the STK600 crystal socket. GCLK0 is GPIO pin 3/pin pa03/pin#7 on a UC3D QFP64 package; for the RCUC3D routing card, this pin is mapped on STK600.PORTA.PA3.
On UC3C_EK, GCLK_0_2 is pin number 54 (PB22) with AT32UC3C0512C in QFP144 package.
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