conf_clock.h File Reference

Clock configuration.

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

Macros
#define	CONFIG_DFLL0_DIV   1
#define	CONFIG_DFLL0_MUL   (48000000UL / OSC_RCSYS_NOMINAL_HZ)
#define	CONFIG_DFLL0_SOURCE   GENCLK_SRC_RCSYS
#define	CONFIG_SYSCLK_CPU_DIV   2 /* Fcpu = Fsys/(2 ^ CPU_div) */
#define	CONFIG_SYSCLK_INIT_PBAMASK   (1 << SYSCLK_USART3)
#define	CONFIG_SYSCLK_PBA_DIV   2 /* Fpba = Fsys/(2 ^ PBA_div) */
#define	CONFIG_SYSCLK_PBB_DIV   2 /* Fpbb = Fsys/(2 ^ PBB_div) */
#define	CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_DFLL

#define CONFIG_DFLL0_DIV   1

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_MUL   (48000000UL / OSC_RCSYS_NOMINAL_HZ)

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_SOURCE   GENCLK_SRC_RCSYS

Referenced by dfll_enable_config_defaults().

#define CONFIG_SYSCLK_CPU_DIV   2 /* Fcpu = Fsys/(2 ^ CPU_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_INIT_PBAMASK   (1 << SYSCLK_USART3)

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBA_DIV   2 /* Fpba = Fsys/(2 ^ PBA_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBB_DIV   2 /* Fpbb = Fsys/(2 ^ PBB_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_DFLL

Note

Clock source - DFLL is used to generate 12MHz CPU clock

Referenced by sysclk_init().