Driver for the SCIF (System Control Interface).
The SCIF controls the oscillators, Generic Clocks, BODs, VREG, Temperature Sensor, and Backup Registers.
Data Structures | |
| struct | scif_dfll_closedloop_conf_t |
| DFLL closed-loop mode settings. More... | |
| struct | scif_dfll_openloop_conf_t |
| DFLL open-loop mode settings. More... | |
| struct | scif_dfll_ssg_conf_t |
| DFLL SSG settings. More... | |
| struct | scif_gclk_opt_t |
| Generic clock generation settings. More... | |
| struct | scif_osc32_opt_t |
| OSC32 startup options. More... | |
| struct | scif_osc_opt_t |
| OSC0/OSC1 startup options. More... | |
Macros | |
| #define | AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE 0x00000000 |
| #define | AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE 0x00000001 |
| #define | AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000 |
| #define | AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001 |
| #define | SCIF_DFLL_MAXFREQ_HZ 150000000UL |
| #define | SCIF_DFLL_MAXFREQ_KHZ 150000 |
| The max DFLL output frequency. More... | |
| #define | SCIF_DFLL_MINFREQ_HZ 40000000UL |
| #define | SCIF_DFLL_MINFREQ_KHZ 40000 |
| The min DFLL output frequency. More... | |
| #define | SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000UL |
| #define | SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000UL |
| Device-specific data. More... | |
| #define | SCIF_NOT_SUPPORTED (-10000) |
| Define "not supported" for the chosen implementation. More... | |
| #define | SCIF_OSC32_FREQ_HZ 32768 |
| The OSC32 frequency. More... | |
| #define | SCIF_POLL_TIMEOUT 100000 |
| The timeguard used for polling in ticks. More... | |
| #define | SCIF_RC120M_FREQ_HZ 120000000UL |
| The RC120M frequency. More... | |
| #define | SCIF_RC120M_FREQ_KHZ 120000 |
| #define | SCIF_RC32K_FREQ_HZ 32768 |
| The RC32K slow clock frequency. More... | |
| #define | SCIF_RC32K_FREQ_KHZ (SCIF_RC32K_FREQ_HZ/1000) |
| #define | SCIF_SLOWCLOCK_FREQ_HZ AVR32_SCIF_RCOSC_FREQUENCY |
| The RCSYS slow clock frequency. More... | |
| #define | SCIF_SLOWCLOCK_FREQ_KHZ (SCIF_SLOWCLOCK_FREQ_HZ/1000) |
| #define | SCIF_UNLOCK(reg) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg)) |
| Unlock SCIF register macro. More... | |
Enumerations | |
| enum | scif_gcctrl_oscsel_t { SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GCCTRL_OSCSEL_RCSYS, SCIF_GCCTRL_OSC32K = AVR32_SCIF_GCCTRL_OSCSEL_OSC32K, SCIF_GCCTRL_DFLL0 = AVR32_SCIF_GCCTRL_OSCSEL_DFLL0, SCIF_GCCTRL_OSC0 = AVR32_SCIF_GCCTRL_OSCSEL_OSC0, SCIF_GCCTRL_RC120M = AVR32_SCIF_GCCTRL_OSCSEL_RC120M, SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GCCTRL_OSCSEL_CLK_CPU, SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GCCTRL_OSCSEL_CLK_HSB, SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GCCTRL_OSCSEL_CLK_PBA, SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GCCTRL_OSCSEL_CLK_PBB, SCIF_GCCTRL_RC32K = AVR32_SCIF_GCCTRL_OSCSEL_RC32K, SCIF_GCCTRL_CLK1K = AVR32_SCIF_GCCTRL_OSCSEL_CLK_1K, SCIF_GCCTRL_OSCSEL_INVALID } |
| The different clock source for the generic clocks. More... | |
| enum | scif_osc_mode_t { SCIF_OSC_MODE_EXT_CLK = 0, SCIF_OSC_MODE_2PIN_CRYSTAL = 1, SCIF_OSC_MODE_NOT_SUPPORTED_1 = 2, SCIF_OSC_MODE_NOT_SUPPORTED_2 = 3, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4, SCIF_OSC_MODE_NOT_SUPPORTED_3 = 5, SCIF_OSC_MODE_NOT_SUPPORTED_4 = 6, SCIF_OSC_MODE_NOT_SUPPORTED_5 = 7 } |
| The different oscillator modes. More... | |
| enum | scif_osc_t { SCIF_OSC0 = 0, SCIF_OSC1 = 1 } |
| The different oscillators. More... | |
Interrupt Functions | |
| static __always_inline void | scif_enable_interrupts (unsigned long mask) |
| Enable SCIF interrupts. More... | |
| static __always_inline void | scif_disable_interrupts (unsigned long mask) |
| Disable SCIF interrupts. More... | |
| static __always_inline unsigned long | scif_get_enabled_interrupts (void) |
| Read the SCIF currently enabled interrupts. More... | |
| static __always_inline unsigned long | scif_get_interrupts_status (void) |
| Read the interrupt status of the SCIF. More... | |
| static __always_inline void | scif_clear_interrupts_status (unsigned long mask) |
| Clear raised interrupts from the SCIF. More... | |
Power and Clocks Status Functions | |
| static __always_inline unsigned long | scif_get_pclk_status (void) |
| Read the Power and Clocks Status of the SCIF. More... | |
OSC0/OSC1 Functions | |
| long int | scif_start_osc (scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready) |
| Configure and start an OSC0/OSC1 oscillator. More... | |
| bool | scif_is_osc_ready (scif_osc_t osc) |
| Is an oscillator stable and ready to be used as clock source? More... | |
| long int | scif_stop_osc (scif_osc_t osc) |
| Stop an oscillator. More... | |
| long int | scif_configure_osc_crystalmode (scif_osc_t osc, unsigned int fcrystal) |
| Configure an oscillator in crystal mode. More... | |
| long int | scif_configure_osc_extmode (scif_osc_t osc) |
| Configure an external clock as input clock. More... | |
| long int | scif_enable_osc (scif_osc_t osc, unsigned int startup, bool wait_for_ready) |
| Enable an oscillator with a given startup time. More... | |
OSC32 Functions | |
| long int | scif_start_osc32 (const scif_osc32_opt_t *opt, bool wait_for_ready) |
| Configure and start the OSC32 oscillator. More... | |
| static __always_inline bool | scif_is_osc32_ready (void) |
| Is OSC32 stable and ready to be used as clock source? More... | |
| static __always_inline void | scif_osc32_1kout_ena (void) |
| Enable the 1kHz output of the OSC32 oscillator. More... | |
| static __always_inline void | scif_osc32_1kout_dis (void) |
| Disable the 1kHz output of the OSC32 oscillator. More... | |
| static __always_inline void | scif_osc32_32kout_ena (void) |
| Enable the 32kHz output of the OSC32 oscillator. More... | |
| static __always_inline void | scif_osc32_32kout_dis (void) |
| Disable the 32kHz output of the OSC32 oscillator. More... | |
| long int | scif_stop_osc32 (void) |
| Stop the OSC32 oscillator. More... | |
DFLL Control Functions | |
| long int | scif_dfll0_openloop_start (const scif_dfll_openloop_conf_t *pdfllconfig) |
| Configure and start the DFLL0 in open loop mode. More... | |
| long int | scif_dfll0_openloop_start_auto (unsigned long TargetFreqkHz) |
| Automatic configuration and start of the DFLL0 in open loop mode. More... | |
| long int | scif_dfll0_openloop_updatefreq (const scif_dfll_openloop_conf_t *pdfllconfig) |
| Update the frequency of the DFLL0 in open loop mode. More... | |
| long int | scif_dfll0_openloop_updatefreq_auto (unsigned long TargetFreq) |
| Automatic configuration to update the frequency of the DFLL0 in open loop mode. More... | |
| long int | scif_dfll0_openloop_stop (void) |
| Stop the DFLL0 in open loop mode. More... | |
| long int | scif_dfll0_ssg_enable (scif_dfll_ssg_conf_t *pssg_conf) |
| Configure and enable the SSG. More... | |
| long int | scif_dfll0_closedloop_start (const scif_dfll_closedloop_conf_t *pdfllconfig) |
| Configure and start the DFLL0 in closed loop mode. More... | |
| long int | scif_dfll0_closedloop_configure_and_start (const scif_gclk_opt_t *gc_dfllif_ref_opt, unsigned long long target_freq_hz, bool enable_ssg) |
| Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode. More... | |
| #define | scif_dfll0_ssg_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLLIF_SSG, pgc_conf) |
| Configure and enable the SSG reference generic clock. More... | |
| #define | scif_dfll0_closedloop_mainref_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLLIF_REF, pgc_conf) |
| Configure and enable the closed-loop mode main reference generic clock. More... | |
| #define | scif_dfll0_closedloop_dither_gc_enable(pgc_conf) scif_dfll0_ssg_gc_enable(pgc_conf) |
| Configure and enable the generic clock used by the closed-loop mode dithering stage and by the SSG. More... | |
120MHz RCosc Functions | |
| void | scif_start_rc120M (void) |
| Start the 120MHz internal RCosc (RC120M) clock. More... | |
| void | scif_stop_rc120M (void) |
| Stop the 120MHz internal RCosc (RC120M) clock. More... | |
32kHz internal RCosc (RC32K) Functions | |
| void | scif_start_rc32k (void) |
| Start the 32kHz internal RCosc (RC32K) clock. More... | |
| void | scif_stop_rc32k (void) |
| Stop the 32kHz internal RCosc (RC32K) clock. More... | |
| void | scif_disable_rc32out (void) |
| Un-force the RC32 signal from being output on the dedicated pin (PA20) More... | |
Generic Clock Functions | |
| long int | scif_start_gclk (unsigned int gclk, const scif_gclk_opt_t *opt) |
| Setup and start a generic clock. More... | |
| long int | scif_stop_gclk (unsigned int gclk) |
| Stop a generic clock. More... | |
| long int | scif_gc_setup (unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor) |
| Setup a generic clock. More... | |
| long int | scif_gc_enable (unsigned int gclk) |
| Enable a generic clock. More... | |
Miscellaneous Functions | |
| long int | scif_pclksr_statushigh_wait (unsigned long statusMask) |
| Wait for a status high in the Power and Clocks status register. More... | |
| #define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE 0x00000000 |
| #define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE 0x00000001 |
| #define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000 |
| #define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001 |
| #define scif_dfll0_closedloop_dither_gc_enable | ( | pgc_conf | ) | scif_dfll0_ssg_gc_enable(pgc_conf) |
Configure and enable the generic clock used by the closed-loop mode dithering stage and by the SSG.
| pgc_conf | The settings for the generic clock [INPUT] |
| 0 | Dithering & SSG reference generic clock configured and started successfully. |
| <0 | Error. |
| #define scif_dfll0_closedloop_mainref_gc_enable | ( | pgc_conf | ) | scif_start_gclk(AVR32_SCIF_GCLK_DFLLIF_REF, pgc_conf) |
Configure and enable the closed-loop mode main reference generic clock.
| pgc_conf | The settings for the generic clock [INPUT] |
| 0 | Main reference generic clock configured and started successfully. |
| <0 | Error. |
Referenced by scif_dfll0_closedloop_configure_and_start().
| #define scif_dfll0_ssg_gc_enable | ( | pgc_conf | ) | scif_start_gclk(AVR32_SCIF_GCLK_DFLLIF_SSG, pgc_conf) |
Configure and enable the SSG reference generic clock.
| pgc_conf | The settings for the generic clock [INPUT] |
| 0 | SSG Generic clock configured and started successfully. |
| <0 | Error. |
| #define SCIF_DFLL_MAXFREQ_HZ 150000000UL |
Referenced by pcl_configure_clocks_dfll0(), and scif_dfll0_closedloop_configure_and_start().
| #define SCIF_DFLL_MAXFREQ_KHZ 150000 |
The max DFLL output frequency.
Referenced by scif_dfll0_openloop_start_auto().
| #define SCIF_DFLL_MINFREQ_HZ 40000000UL |
Referenced by pcl_configure_clocks_dfll0(), and scif_dfll0_closedloop_configure_and_start().
| #define SCIF_DFLL_MINFREQ_KHZ 40000 |
The min DFLL output frequency.
Referenced by scif_dfll0_openloop_start_auto().
| #define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000UL |
Referenced by scif_start_osc(), and scif_start_osc32().
| #define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000UL |
Device-specific data.
< External crystal/clock min frequency (in Herz) External crystal/clock max frequency (in Herz)
Referenced by scif_start_osc(), and scif_start_osc32().
| #define SCIF_NOT_SUPPORTED (-10000) |
Define "not supported" for the chosen implementation.
| #define SCIF_OSC32_FREQ_HZ 32768 |
The OSC32 frequency.
| #define SCIF_POLL_TIMEOUT 100000 |
The timeguard used for polling in ticks.
Referenced by scif_pclksr_statushigh_wait(), and scif_stop_gclk().
| #define SCIF_RC120M_FREQ_HZ 120000000UL |
The RC120M frequency.
Referenced by pcl_configure_clocks_rc120m(), and scif_dfll0_closedloop_configure_and_start().
| #define SCIF_RC120M_FREQ_KHZ 120000 |
| #define SCIF_RC32K_FREQ_HZ 32768 |
The RC32K slow clock frequency.
Referenced by scif_dfll0_closedloop_configure_and_start().
| #define SCIF_RC32K_FREQ_KHZ (SCIF_RC32K_FREQ_HZ/1000) |
| #define SCIF_SLOWCLOCK_FREQ_HZ AVR32_SCIF_RCOSC_FREQUENCY |
The RCSYS slow clock frequency.
Referenced by pcl_configure_clocks_rcsys(), and scif_dfll0_closedloop_configure_and_start().
| #define SCIF_SLOWCLOCK_FREQ_KHZ (SCIF_SLOWCLOCK_FREQ_HZ/1000) |
| #define SCIF_UNLOCK | ( | reg | ) | (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg)) |
Unlock SCIF register macro.
Referenced by scif_configure_osc_crystalmode(), scif_configure_osc_extmode(), scif_dfll0_closedloop_start(), scif_dfll0_openloop_start(), scif_dfll0_openloop_stop(), scif_dfll0_openloop_updatefreq(), scif_dfll0_ssg_enable(), scif_enable_osc(), scif_pll0_disable(), scif_pll0_enable(), scif_pll0_setup(), scif_start_osc(), scif_start_osc32(), scif_start_rc120M(), scif_start_rc32k(), scif_stop_osc(), scif_stop_osc32(), scif_stop_rc120M(), and scif_stop_rc32k().
| enum scif_gcctrl_oscsel_t |
The different clock source for the generic clocks.
| enum scif_osc_mode_t |
| enum scif_osc_t |
|
static |
Clear raised interrupts from the SCIF.
| mask | The interrupts to clear. |
| long int scif_configure_osc_crystalmode | ( | scif_osc_t | osc, |
| unsigned int | fcrystal | ||
| ) |
Configure an oscillator in crystal mode.
| osc | The oscillator to configure [INPUT] |
| fcrystal | Crystal frequency (Hz) [INPUT] |
| 0 | Oscillator successfully configured. |
| <0 | Error configuring the oscillator. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, PASS, SCIF_OSC_MODE_2PIN_CRYSTAL, and SCIF_UNLOCK.
Referenced by pcl_configure_clocks_osc0(), and pcl_switch_to_osc().
| long int scif_configure_osc_extmode | ( | scif_osc_t | osc | ) |
Configure an external clock as input clock.
| osc | The external clock to configure [INPUT] |
| 0 | External clock successfully configured. |
| <0 | Error configuring the external clock. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, PASS, SCIF_OSC_MODE_EXT_CLK, and SCIF_UNLOCK.
| long int scif_dfll0_closedloop_configure_and_start | ( | const scif_gclk_opt_t * | gc_dfllif_ref_opt, |
| unsigned long long | target_freq_hz, | ||
| bool | enable_ssg | ||
| ) |
Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.
| gc_dfllif_ref_opt | The settings for the CLK_DFLLIF_REF generic clock [INPUT] |
| target_freq_hz | The target frequency (in Hz) [INPUT] |
| enable_ssg | Enable/disable the SSG feature [INPUT] |
| 0 | DFLL0 configured and started successfully. |
| <0 | Error. |
References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, scif_gclk_opt_t::extosc_f, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::imul, PASS, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_CLK1K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_SLOWCLOCK, SCIF_RC120M_FREQ_HZ, SCIF_RC32K_FREQ_HZ, and SCIF_SLOWCLOCK_FREQ_HZ.
Referenced by pcl_configure_clocks_dfll0().
| long int scif_dfll0_closedloop_start | ( | const scif_dfll_closedloop_conf_t * | pdfllconfig | ) |
Configure and start the DFLL0 in closed loop mode.
| pdfllconfig | The DFLL parameters in closed loop mode [INPUT] |
| 0 | DFLL0 configured and started successfully. |
| <0 | Error. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, ENABLE, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::imul, PASS, SCIF_DFLL0_MODE_CLOSEDLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
Referenced by scif_dfll0_closedloop_configure_and_start().
| long int scif_dfll0_openloop_start | ( | const scif_dfll_openloop_conf_t * | pdfllconfig | ) |
Configure and start the DFLL0 in open loop mode.
| pdfllconfig | The DFLL parameters in open loop mode [INPUT] |
| 0 | DFLL0 configured and started successfully. |
| <0 | Error. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, ENABLE, scif_dfll_openloop_conf_t::fine, PASS, SCIF_DFLL0_MODE_OPENLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
Referenced by scif_dfll0_openloop_start_auto().
| long int scif_dfll0_openloop_start_auto | ( | unsigned long | TargetFreqkHz | ) |
Automatic configuration and start of the DFLL0 in open loop mode.
| TargetFreqkHz | The DFLL target frequency (in kHz) [INPUT] |
| 0 | DFLL0 configured and started successfully. |
| <0 | Error. |
References scif_dfll_openloop_conf_t::coarse, scif_dfll_openloop_conf_t::fine, scif_dfll0_openloop_start(), SCIF_DFLL_COARSE_MAX, SCIF_DFLL_FINE_HALF, SCIF_DFLL_FINE_MAX, SCIF_DFLL_MAXFREQ_KHZ, and SCIF_DFLL_MINFREQ_KHZ.
| long int scif_dfll0_openloop_stop | ( | void | ) |
Stop the DFLL0 in open loop mode.
| 0 | DFLL0 successfully stopped. |
| <0 | Error. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, PASS, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
| long int scif_dfll0_openloop_updatefreq | ( | const scif_dfll_openloop_conf_t * | pdfllconfig | ) |
Update the frequency of the DFLL0 in open loop mode.
| pdfllconfig | The DFLL parameters in open loop mode [INPUT] |
| 0 | DFLL0 frequency updated successfully. |
| <0 | Error. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, PASS, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
| long int scif_dfll0_openloop_updatefreq_auto | ( | unsigned long | TargetFreq | ) |
Automatic configuration to update the frequency of the DFLL0 in open loop mode.
| TargetFreq | The DFLL target frequency (in kHz) [INPUT] |
| 0 | DFLL0 frequency updated successfully. |
| <0 | Error. |
| long int scif_dfll0_ssg_enable | ( | scif_dfll_ssg_conf_t * | pssg_conf | ) |
Configure and enable the SSG.
| pssg_conf | The settings for the SCIF.DFLL0SSG register [INPUT] |
| 0 | SSG Generic clock configured and started successfully. |
| <0 | Error. |
References scif_dfll_ssg_conf_t::amplitude, AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, u_avr32_scif_dfll0ssg_t::dfll0ssg, u_avr32_scif_dfll0ssg_t::DFLL0SSG, ENABLE, PASS, SCIF_UNLOCK, scif_dfll_ssg_conf_t::step_size, and scif_dfll_ssg_conf_t::use_random.
|
static |
Disable SCIF interrupts.
| mask | the interrupts to disable. |
| void scif_disable_rc32out | ( | void | ) |
Un-force the RC32 signal from being output on the dedicated pin (PA20)
References AVR32_ENTER_CRITICAL_REGION, and AVR32_LEAVE_CRITICAL_REGION.
Referenced by scif_start_osc32().
|
static |
Enable SCIF interrupts.
| mask | the interrupts to enable. |
| long int scif_enable_osc | ( | scif_osc_t | osc, |
| unsigned int | startup, | ||
| bool | wait_for_ready | ||
| ) |
Enable an oscillator with a given startup time.
| osc | The oscillator to configure [INPUT] |
| startup | Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT] |
| wait_for_ready | Wait for the oscillator to be stable before return [INPUT] |
| 0 | Oscillator successfully started |
| <0 | Error starting the oscillator. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, ENABLE, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, PASS, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
Referenced by pcl_configure_clocks_osc0(), and pcl_switch_to_osc().
| long int scif_gc_enable | ( | unsigned int | gclk | ) |
Enable a generic clock.
| gclk | generic clock number (0 for gc0...) |
| 0 | Success. |
| <0 | An error occurred. |
References PASS.
Referenced by pcl_configure_usb_clock().
| long int scif_gc_setup | ( | unsigned int | gclk, |
| scif_gcctrl_oscsel_t | clk_src, | ||
| unsigned int | diven, | ||
| unsigned int | divfactor | ||
| ) |
Setup a generic clock.
| gclk | generic clock number (0 for gc0...) |
| clk_src | The input clock source to use for the generic clock |
| diven | Generic clock divisor enable |
| divfactor | Generic clock divisor |
| 0 | Success. |
| <0 | An error occurred. |
References PASS, SCIF_GCCTRL_OSCSEL_INVALID, and scif_stop_gclk().
Referenced by pcl_configure_usb_clock().
|
static |
Read the SCIF currently enabled interrupts.
|
static |
Read the interrupt status of the SCIF.
|
static |
Read the Power and Clocks Status of the SCIF.
|
static |
Is OSC32 stable and ready to be used as clock source?
| true | oscillator stable and ready |
| false | oscillator not enabled or not ready. |
| bool scif_is_osc_ready | ( | scif_osc_t | osc | ) |
Is an oscillator stable and ready to be used as clock source?
| osc | The oscillator [INPUT] |
| true | oscillator stable and ready |
| false | oscillator not enabled or not ready. |
|
static |
Disable the 1kHz output of the OSC32 oscillator.
|
static |
Enable the 1kHz output of the OSC32 oscillator.
|
static |
Disable the 32kHz output of the OSC32 oscillator.
|
static |
Enable the 32kHz output of the OSC32 oscillator.
| long int scif_pclksr_statushigh_wait | ( | unsigned long | statusMask | ) |
Wait for a status high in the Power and Clocks status register.
| statusMask | Mask field of the status to poll [INPUT] |
| 0 | Status is high. |
| <0 | SCIF_POLL_TIMEOUT Timeout expired before the status was high. |
Wait for a status high in the Power and Clocks status register.
Misc
Wait for a status high in the Power and Clocks status register.
| statusMask | Mask field of the status to poll [INPUT] |
| 0 | Status is high. |
| <0 | SCIF_POLL_TIMEOUT Timeout expired before the status was high. |
References PASS, and SCIF_POLL_TIMEOUT.
Referenced by scif_dfll0_closedloop_start(), scif_dfll0_openloop_start(), scif_dfll0_openloop_stop(), scif_dfll0_openloop_updatefreq(), scif_enable_osc(), scif_start_osc(), and scif_start_osc32().
| long int scif_start_gclk | ( | unsigned int | gclk, |
| const scif_gclk_opt_t * | opt | ||
| ) |
Setup and start a generic clock.
| gclk | The generic clock number to setup and start (cf. datasheet) |
| opt | The settings for the generic clock. |
| 0 | Success. |
| <0 | An error occurred. |
Setup and start a generic clock.
References scif_gclk_opt_t::clock_source, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, PASS, and SCIF_GCCTRL_OSCSEL_INVALID.
| long int scif_start_osc | ( | scif_osc_t | osc, |
| const scif_osc_opt_t * | opt, | ||
| bool | wait_for_ready | ||
| ) |
Configure and start an OSC0/OSC1 oscillator.
| osc | The oscillator to start [INPUT] |
| opt | The configuration of the oscillator [INPUT] |
| wait_for_ready | Wait for the oscillator to be stable before return [INPUT] |
| 0 | Oscillator start successful. |
| <0 | Error starting the oscillator. |
Configure and start an OSC0/OSC1 oscillator.
Power and Clocks Status Functions OSC0/OSC1 Functions
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, ENABLE, scif_osc_opt_t::freq_hz, scif_osc_opt_t::gain, scif_osc_opt_t::mode, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, PASS, SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc_opt_t::startup.
| long int scif_start_osc32 | ( | const scif_osc32_opt_t * | opt, |
| bool | wait_for_ready | ||
| ) |
Configure and start the OSC32 oscillator.
| opt | The configuration of the oscillator [INPUT] |
| wait_for_ready | Wait for the oscillator to be stable before return [INPUT] |
| 0 | Oscillator start successful. |
| <0 | Error starting the oscillator. |
Configure and start the OSC32 oscillator.
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, scif_osc32_opt_t::en1k, scif_osc32_opt_t::en32k, ENABLE, scif_osc32_opt_t::mode, u_avr32_scif_oscctrl32_t::oscctrl32, u_avr32_scif_oscctrl32_t::OSCCTRL32, PASS, scif_osc32_opt_t::pinsel, scif_disable_rc32out(), SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc32_opt_t::startup.
| void scif_start_rc120M | ( | void | ) |
Start the 120MHz internal RCosc (RC120M) clock.
Start the 120MHz internal RCosc (RC120M) clock.
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, and SCIF_UNLOCK.
Referenced by pcl_configure_clocks_rc120m().
| void scif_start_rc32k | ( | void | ) |
Start the 32kHz internal RCosc (RC32K) clock.
Start the 32kHz internal RCosc (RC32K) clock.
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, and SCIF_UNLOCK.
| long int scif_stop_gclk | ( | unsigned int | gclk | ) |
Stop a generic clock.
| gclk | The generic clock number to stop. |
| 0 | Success. |
| <0 | Unable to stop generic clock. |
References PASS, and SCIF_POLL_TIMEOUT.
Referenced by scif_gc_setup().
| long int scif_stop_osc | ( | scif_osc_t | osc | ) |
Stop an oscillator.
| osc | The oscillator to stop |
| 0 | Oscillator successfully stopped. |
| <0 | An error occurred when stopping the oscillator. |
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, PASS, and SCIF_UNLOCK.
| long int scif_stop_osc32 | ( | void | ) |
Stop the OSC32 oscillator.
| 0 | Oscillator successfully stopped. |
| <0 | An error occurred when stopping the oscillator. |
References PASS, and SCIF_UNLOCK.
| void scif_stop_rc120M | ( | void | ) |
Stop the 120MHz internal RCosc (RC120M) clock.
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, and SCIF_UNLOCK.
| void scif_stop_rc32k | ( | void | ) |
Stop the 32kHz internal RCosc (RC32K) clock.
References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, and SCIF_UNLOCK.
1.8.5