These macros manage the common features of the pipes.
| #define Host_ack_all_errors | ( | p | ) |
acks all pipe error
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Host_ack_bad_data_toggle | ( | p | ) | (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATATGL_MASK)) |
acks bad data toggle
| #define Host_ack_control_in_received | ( | ) | (AVR32_USBB_upstaxclr(P_CONTROL) = AVR32_USBB_UPSTAXCLR_RXINIC_MASK) |
acks control IN
Referenced by host_transfer_control().
| #define Host_ack_control_in_received_free | ( | ) | (Host_ack_control_in_received(), Host_free_control_in()) |
acks control IN and frees current bank
Referenced by host_transfer_control().
| #define Host_ack_control_out_ready | ( | ) | (AVR32_USBB_upstaxclr(P_CONTROL) = AVR32_USBB_UPSTAXCLR_TXOUTIC_MASK) |
acks control OUT
Referenced by host_transfer_control().
| #define Host_ack_control_out_ready_send | ( | ) | (Host_ack_control_out_ready(), Host_send_control_out()) |
acks control OUT and sends current bank
Referenced by host_transfer_control().
| #define Host_ack_crc16_error | ( | p | ) | (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_CRC16_MASK)) |
acks CRC16 error
| #define Host_ack_crc_error | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_RXSTALLDIC_MASK) |
acks CRC ERROR ISO IN detected
| #define Host_ack_data_pid_error | ( | p | ) | (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATAPID_MASK)) |
acks data PID error
| #define Host_ack_fifocon | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_FIFOCONC_MASK) |
clears FIFOCON bit
| #define Host_ack_in_received | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_RXINIC_MASK) |
acks IN reception
Referenced by host_get_data().
| #define Host_ack_in_received_free | ( | p | ) | (Host_ack_in_received(p), Host_free_in(p)) |
acks IN reception and frees current bank
| #define Host_ack_nak_received | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_NAKEDIC_MASK) |
acks NAK received
Referenced by host_get_data(), and host_send_data().
| #define Host_ack_out_ready | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_TXOUTIC_MASK) |
acks OUT sent
Referenced by host_send_data().
| #define Host_ack_out_ready_send | ( | p | ) | (Host_ack_out_ready(p), Host_send_out(p)) |
acks OUT sent and sends current bank
Referenced by host_send_data().
| #define Host_ack_overflow_interrupt | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_OVERFIC_MASK) |
acks pipe overflow interrupt
| #define Host_ack_pid_error | ( | p | ) | (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_PID_MASK)) |
acks PID error
| #define Host_ack_pipe_error | ( | p | ) | (AVR32_USBB_upstaxset(p) = (Is_host_pipe_error(p)) ? AVR32_USBB_UPSTAXSET_PERRIS_MASK : 0) |
acks pipe error
| #define Host_ack_setup_ready | ( | ) | (AVR32_USBB_upstaxclr(P_CONTROL) = AVR32_USBB_UPSTAXCLR_TXSTPIC_MASK) |
acks setup
Referenced by host_transfer_control().
| #define Host_ack_setup_ready_send | ( | ) | (Host_ack_setup_ready(), Host_send_setup()) |
acks setup and sends current bank
| #define Host_ack_short_packet | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_SHORTPACKETIC_MASK) |
acks SHORT PACKET received
| #define Host_ack_stall | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_RXSTALLDIC_MASK) |
acks STALL reception
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Host_ack_timeout_error | ( | p | ) | (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_TIMEOUT_MASK)) |
acks time-out error
| #define Host_ack_underflow_interrupt | ( | p | ) | (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_TXSTPIC_MASK) |
acks pipe underflow interrupt
| #define Host_allocate_memory | ( | p | ) | (Set_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_ALLOC_MASK)) |
allocates the configuration x in DPRAM memory
| #define Host_byte_count | ( | p | ) | (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_PBYCT_MASK)) |
returns the byte count
Referenced by host_get_data(), host_read_p_rxpacket(), host_set_p_txpacket(), host_transfer_control(), and host_write_p_txpacket().
| #define Host_clear_error_counter | ( | p | ) | (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_COUNTER_MASK)) |
clears the error counter
| #define Host_configure_pipe | ( | p, | |
| freq, | |||
| ep_num, | |||
| type, | |||
| token, | |||
| size, | |||
| bank | |||
| ) |
configures selected pipe in one step
Referenced by host_check_class(), and usb_host_task().
| #define Host_configure_pipe_bank | ( | p, | |
| bank | |||
| ) | (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PBK_MASK, bank)) |
configures the selected pipe number of banks
| #define Host_configure_pipe_endpoint_number | ( | p, | |
| ep_num | |||
| ) | (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PEPNUM_MASK, ep_num)) |
configures the selected pipe endpoint number
| #define Host_configure_pipe_int_req_freq | ( | p, | |
| freq | |||
| ) | (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_INTFRQ_MASK, freq)) |
configures the interrupt pipe request frequency (period in ms) for the selected pipe
Referenced by host_check_class().
| #define Host_configure_pipe_size | ( | p, | |
| size | |||
| ) | (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PSIZE_MASK, Host_format_pipe_size(size))) |
configures the selected pipe size
| #define Host_configure_pipe_token | ( | p, | |
| token | |||
| ) | (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTOKEN_MASK, token)) |
configures the selected pipe token
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Host_configure_pipe_type | ( | p, | |
| type | |||
| ) | (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTYPE_MASK, type)) |
configures the selected pipe type
| #define Host_current_bank | ( | p | ) | (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_CURRBK_MASK)) |
returns the number of the current bank
| #define Host_data_toggle | ( | p | ) | (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_DTSEQ_MASK)) |
returns data toggle
| #define Host_disable_bank_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_NBUSYBKEC_MASK) |
disables all banks full (IN) or free (OUT) interrupt
| #define Host_disable_continuous_in_mode | ( | p | ) | (Clr_bits(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INMODE_MASK)) |
disables continuous IN mode
Referenced by host_transfer_control().
| #define Host_disable_control_in_received_interrupt | ( | ) | (AVR32_USBB_upconxclr(P_CONTROL) = AVR32_USBB_UPCONXCLR_RXINEC_MASK) |
disables IN control pipe reception interrupt
| #define Host_disable_control_out_ready_interrupt | ( | ) | (AVR32_USBB_upconxclr(P_CONTROL) = AVR32_USBB_UPCONXCLR_TXOUTEC_MASK) |
disables OUT control pipe ready interrupt
| #define Host_disable_crc_error_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_RXSTALLDEC_MASK) |
disables CRC ERROR ISO IN detected interrupt
| #define Host_disable_in_received_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_RXINEC_MASK) |
disables IN pipe reception interrupt
| #define Host_disable_nak_received_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_NAKEDEC_MASK) |
disables NAK received interrupt
| #define Host_disable_out_ready_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_TXOUTEC_MASK) |
disables OUT pipe ready interrupt
| #define Host_disable_overflow_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_OVERFIEC_MASK) |
disables overflow interrupt
| #define Host_disable_pipe | ( | p | ) | (Clr_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PEN0_MASK << (p))) |
disables the selected pipe
Referenced by host_check_class(), host_disable_all_pipes(), and usb_host_task().
| #define Host_disable_pipe_bank_autoswitch | ( | p | ) | (Clr_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_AUTOSW_MASK)) |
disables the bank autoswitch for the selected pipe
| #define Host_disable_pipe_error_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_PERREC_MASK) |
disables pipe error interrupt
| #define Host_disable_pipe_interrupt | ( | p | ) | (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_P0INTEC_MASK << (p)) |
disables the selected pipe interrupt
Referenced by host_disable_all_pipes().
| #define Host_disable_setup_ready_interrupt | ( | ) | (AVR32_USBB_upconxclr(P_CONTROL) = AVR32_USBB_UPCONXCLR_TXSTPEC_MASK) |
disables SETUP pipe ready interrupt
| #define Host_disable_short_packet_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_SHORTPACKETIEC_MASK) |
disables SHORT PACKET received interrupt
| #define Host_disable_stall_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_RXSTALLDEC_MASK) |
disables STALL received interrupt
| #define Host_disable_underflow_interrupt | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_TXSTPEC_MASK) |
disables underflow interrupt
| #define Host_enable_bank_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_NBUSYBKES_MASK) |
enables all banks full (IN) or free (OUT) interrupt
| #define Host_enable_continuous_in_mode | ( | p | ) | (Set_bits(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INMODE_MASK)) |
enables continuous IN mode
Referenced by host_get_data().
| #define Host_enable_control_in_received_interrupt | ( | ) | (AVR32_USBB_upconxset(P_CONTROL) = AVR32_USBB_UPCONXSET_RXINES_MASK) |
enables IN control pipe reception interrupt
| #define Host_enable_control_out_ready_interrupt | ( | ) | (AVR32_USBB_upconxset(P_CONTROL) = AVR32_USBB_UPCONXSET_TXOUTES_MASK) |
enables OUT control pipe ready interrupt
| #define Host_enable_crc_error_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RXSTALLDES_MASK) |
enables CRC ERROR ISO IN detected interrupt
| #define Host_enable_in_received_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RXINES_MASK) |
enables IN pipe reception interrupt
| #define Host_enable_nak_received_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_NAKEDES_MASK) |
enables NAK received interrupt
| #define Host_enable_out_ready_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_TXOUTES_MASK) |
enables OUT pipe ready interrupt
| #define Host_enable_overflow_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_OVERFIES_MASK) |
enables overflow interrupt
| #define Host_enable_ping | ( | p | ) | (Set_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PINGEN_MASK)) |
Enable PING management for the endpoint p.
Referenced by host_check_class().
| #define Host_enable_pipe | ( | p | ) | (Set_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PEN0_MASK << (p))) |
enables the selected pipe
Referenced by host_check_class(), and usb_host_task().
| #define Host_enable_pipe_bank_autoswitch | ( | p | ) | (Set_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_AUTOSW_MASK)) |
enables the bank autoswitch for the selected pipe
| #define Host_enable_pipe_error_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_PERRES_MASK) |
enables pipe error interrupt
| #define Host_enable_pipe_interrupt | ( | p | ) | (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_P0INTES_MASK << (p)) |
enables the selected pipe interrupt
| #define Host_enable_setup_ready_interrupt | ( | ) | (AVR32_USBB_upconxset(P_CONTROL) = AVR32_USBB_UPCONXSET_TXSTPES_MASK) |
enables SETUP pipe ready interrupt
| #define Host_enable_short_packet_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_SHORTPACKETIES_MASK) |
enables SHORT PACKET received interrupt
| #define Host_enable_stall_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RXSTALLDES_MASK) |
enables STALL received interrupt
| #define Host_enable_underflow_interrupt | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_TXSTPES_MASK) |
enables underflow interrupt
| #define Host_error_status | ( | p | ) |
tests if error occurs on pipe
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Host_force_bank_interrupt | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_NBUSYBKS_MASK) |
forces all banks full (OUT) or free (IN) interrupt
Bounds given integer size to allowed range and rounds it up to the nearest available greater size, then applies register format of USBB controller for pipe size bit-field.
| #define Host_free_control_in | ( | ) | (Host_ack_fifocon(P_CONTROL)) |
frees current bank for IN control pipe
Referenced by host_transfer_control().
| #define Host_free_in | ( | p | ) | (Host_ack_fifocon(p)) |
frees current bank for IN pipe
Referenced by host_get_data().
| #define Host_freeze_pipe | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_PFREEZES_MASK) |
freezes the pipe
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Host_get_error_counter | ( | p | ) | (Rd_bitfield(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_COUNTER_MASK)) |
| #define Host_get_in_request_number | ( | p | ) | (Rd_bitfield(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INRQ_MASK) + 1) |
returns number of remaining IN requests
| #define Host_get_interrupt_pipe_number | ( | ) |
returns the lowest pipe number generating a pipe interrupt or MAX_PEP_NB if none
Referenced by usb_general_interrupt_non_naked().
| #define Host_get_pipe_bank | ( | p | ) | (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PBK_MASK)) |
gets the configured selected pipe number of banks
| #define Host_get_pipe_endpoint_number | ( | p | ) | (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PEPNUM_MASK)) |
gets the configured selected pipe endpoint number
| #define Host_get_pipe_fifo_access | ( | p, | |
| scale | |||
| ) | (AVR32_USBB_FIFOX_DATA(p, scale)) |
Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected pipe.
| p | Pipe of which to access FIFO data register |
| scale | Data scale in bits: 64, 32, 16 or 8 |
| #define Host_get_pipe_int_req_freq | ( | p | ) | (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_INTFRQ_MASK)) |
gets the configured interrupt pipe request frequency (period in ms) for the selected pipe
| #define Host_get_pipe_size | ( | p | ) | (8 << Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PSIZE_MASK)) |
gets the configured selected pipe size
Referenced by host_get_data(), host_set_p_txpacket(), host_transfer_control(), and host_write_p_txpacket().
| #define Host_get_pipe_token | ( | p | ) | (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTOKEN_MASK)) |
gets the configured selected pipe token
Referenced by host_check_class().
| #define Host_get_pipe_type | ( | p | ) | (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTYPE_MASK)) |
gets the configured selected pipe type
Referenced by host_check_class(), and usb_general_interrupt_non_naked().
| #define Host_in_request_number | ( | p, | |
| in_num | |||
| ) | (Wr_bitfield(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INRQ_MASK, (in_num) - 1)) |
sets number of IN requests to perform before freeze
| #define Host_nb_busy_bank | ( | p | ) | (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_NBUSYBK_MASK)) |
returns the number of busy banks
Referenced by host_send_data().
| #define Host_raise_control_in_received | ( | ) | (AVR32_USBB_upstaxset(P_CONTROL) = AVR32_USBB_UPSTAXSET_RXINIS_MASK) |
raises control IN
| #define Host_raise_control_out_ready | ( | ) | (AVR32_USBB_upstaxset(P_CONTROL) = AVR32_USBB_UPSTAXSET_TXOUTIS_MASK) |
raises control OUT
| #define Host_raise_crc_error | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_RXSTALLDIS_MASK) |
raises CRC ERROR ISO IN detected
| #define Host_raise_in_received | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_RXINIS_MASK) |
raises IN reception
| #define Host_raise_nak_received | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_NAKEDIS_MASK) |
raises NAK received
| #define Host_raise_out_ready | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_TXOUTIS_MASK) |
raises OUT sent
| #define Host_raise_overflow_interrupt | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_OVERFIS_MASK) |
raises pipe overflow interrupt
| #define Host_raise_pipe_error | ( | p | ) | (AVR32_USBB_upstaxset(p) = (Is_host_pipe_error(p)) ? 0 : AVR32_USBB_UPSTAXSET_PERRIS_MASK) |
raises pipe error
| #define Host_raise_setup_ready | ( | ) | (AVR32_USBB_upstaxset(P_CONTROL) = AVR32_USBB_UPSTAXSET_TXSTPIS_MASK) |
raises setup
| #define Host_raise_short_packet | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_SHORTPACKETIS_MASK) |
raises SHORT PACKET received
| #define Host_raise_stall | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_RXSTALLDIS_MASK) |
raises STALL reception
| #define Host_raise_underflow_interrupt | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_TXSTPIS_MASK) |
raises pipe underflow interrupt
| #define Host_read_pipe_data | ( | p, | |
| scale | |||
| ) |
Read 64-, 32-, 16- or 8-bit data from FIFO data register of selected pipe.
| p | Pipe of which to access FIFO data register |
| scale | Data scale in bits: 64, 32, 16 or 8 |
| #define Host_read_pipe_indexed_data | ( | p, | |
| scale, | |||
| index | |||
| ) | (AVR32_USBB_FIFOX_DATA(p, scale)[(index)]) |
Read 64-, 32-, 16- or 8-bit indexed data from FIFO data register of selected pipe.
| p | Pipe of which to access FIFO data register |
| scale | Data scale in bits: 64, 32, 16 or 8 |
| index | Index of scaled data array to access |
| #define Host_reset_data_toggle | ( | p | ) | (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RSTDTS_MASK) |
resets the data toggle sequence
| #define Host_reset_pipe | ( | p | ) |
resets the selected pipe
Referenced by host_disable_all_pipes(), host_get_data(), host_send_data(), host_transfer_control(), and usb_general_interrupt_non_naked().
| #define Host_reset_pipe_fifo_access | ( | p | ) | (pep_fifo[(p)].u64ptr = Host_get_pipe_fifo_access(p, 64)) |
Reset known position inside FIFO data register of selected pipe.
| p | Pipe of which to reset known position |
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Host_send_control_out | ( | ) | (Host_ack_fifocon(P_CONTROL)) |
sends current bank for OUT control pipe
Referenced by host_transfer_control().
| #define Host_send_out | ( | p | ) | (Host_ack_fifocon(p)) |
sends current bank for OUT pipe
| #define Host_send_setup | ( | ) | (Host_ack_fifocon(P_CONTROL)) |
sends current bank for SETUP pipe
Referenced by host_transfer_control().
| #define Host_unallocate_memory | ( | p | ) | (Clr_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_ALLOC_MASK)) |
un-allocates the configuration x in DPRAM memory
Referenced by host_check_class(), host_disable_all_pipes(), and usb_host_task().
| #define Host_unforce_bank_interrupt | ( | p | ) | (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_NBUSYBKS_MASK) |
unforces all banks full (OUT) or free (IN) interrupt
| #define Host_unfreeze_pipe | ( | p | ) | (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_PFREEZEC_MASK) |
unfreezees the pipe
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Host_write_pipe_data | ( | p, | |
| scale, | |||
| data | |||
| ) |
Write 64-, 32-, 16- or 8-bit data to FIFO data register of selected pipe.
| p | Pipe of which to access FIFO data register |
| scale | Data scale in bits: 64, 32, 16 or 8 |
| data | 64-, 32-, 16- or 8-bit data to write |
Referenced by host_transfer_control().
| #define Host_write_pipe_indexed_data | ( | p, | |
| scale, | |||
| index, | |||
| data | |||
| ) | (AVR32_USBB_FIFOX_DATA(p, scale)[(index)] = (data)) |
Write 64-, 32-, 16- or 8-bit indexed data to FIFO data register of selected pipe.
| p | Pipe of which to access FIFO data register |
| scale | Data scale in bits: 64, 32, 16 or 8 |
| index | Index of scaled data array to access |
| data | 64-, 32-, 16- or 8-bit data to write |
| #define Is_host_bad_data_toggle | ( | p | ) | (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATATGL_MASK)) |
| #define Is_host_bank_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_NBUSYBKE_MASK)) |
tests if all banks full (IN) or free (OUT) interrupt is enabled
| #define Is_host_continuous_in_mode_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INMODE_MASK)) |
tests if continuous IN mode is enabled
| #define Is_host_control_in_filled | ( | ) | (Is_host_fifocon(P_CONTROL)) |
tests if IN received in current bank for control pipe
| #define Is_host_control_in_received | ( | ) | (Tst_bits(AVR32_USBB_upstax(P_CONTROL), AVR32_USBB_UPSTAX_RXINI_MASK)) |
tests if control IN has been received
Referenced by host_transfer_control().
| #define Is_host_control_in_received_interrupt_enabled | ( | ) | (Tst_bits(AVR32_USBB_upconx(P_CONTROL), AVR32_USBB_UPCONX_RXINE_MASK)) |
tests if IN control pipe reception interrupt is enabled
| #define Is_host_control_out_ready | ( | ) | (Tst_bits(AVR32_USBB_upstax(P_CONTROL), AVR32_USBB_UPSTAX_TXOUTI_MASK)) |
tests if control OUT has been sent
Referenced by host_transfer_control().
| #define Is_host_control_out_ready_interrupt_enabled | ( | ) | (Tst_bits(AVR32_USBB_upconx(P_CONTROL), AVR32_USBB_UPCONX_TXOUTE_MASK)) |
tests if OUT control pipe ready interrupt is enabled
| #define Is_host_control_out_sent | ( | ) | (Is_host_fifocon(P_CONTROL)) |
tests if current bank sent for OUT control pipe
| #define Is_host_crc16_error | ( | p | ) | (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_CRC16_MASK)) |
| #define Is_host_crc_error | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RXSTALLDI_MASK)) |
tests if CRC ERROR ISO IN detected
| #define Is_host_crc_error_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RXSTALLDE_MASK)) |
tests if CRC ERROR ISO IN detected interrupt is enabled
| #define Is_host_data_pid_error | ( | p | ) | (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATAPID_MASK)) |
| #define Is_host_data_toggle_reset | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RSTDT_MASK)) |
tests if the data toggle sequence is being reset
| #define Is_host_fifocon | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_FIFOCON_MASK)) |
tests if FIFOCON bit set
| #define Is_host_in_filled | ( | p | ) | (Is_host_fifocon(p)) |
tests if IN received in current bank
| #define Is_host_in_received | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RXINI_MASK)) |
tests if IN received
Referenced by host_get_data().
| #define Is_host_in_received_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RXINE_MASK)) |
tests if IN pipe reception interrupt is enabled
| #define Is_host_memory_allocated | ( | p | ) | (Tst_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_ALLOC_MASK)) |
| #define Is_host_nak_received | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_NAKEDI_MASK)) |
tests if NAK handshake has been received
Referenced by host_get_data(), and host_send_data().
| #define Is_host_nak_received_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_NAKEDE_MASK)) |
tests if NAK received interrupt is enabled
| #define Is_host_out_ready | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_TXOUTI_MASK)) |
tests if OUT has been sent
Referenced by host_send_data().
| #define Is_host_out_ready_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_TXOUTE_MASK)) |
tests if OUT pipe ready interrupt is enabled
| #define Is_host_out_sent | ( | p | ) | (Is_host_fifocon(p)) |
tests if current bank sent for OUT pipe
| #define Is_host_overflow | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_OVERFI_MASK)) |
tests if an overflow occurs
| #define Is_host_overflow_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_OVERFIE_MASK)) |
tests if overflow interrupt is enabled
| #define Is_host_pid_error | ( | p | ) | (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_PID_MASK)) |
| #define Is_host_pipe_bank_autoswitch_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_AUTOSW_MASK)) |
| #define Is_host_pipe_configured | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_CFGOK_MASK)) |
tests if current pipe is configured
| #define Is_host_pipe_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PEN0_MASK << (p))) |
tests if the selected pipe is enabled
Referenced by host_check_class(), and host_disable_all_pipes().
| #define Is_host_pipe_error | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_PERRI_MASK)) |
tests if an error occurs on current pipe
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Is_host_pipe_error_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_PERRE_MASK)) |
tests if pipe error interrupt is enabled
| #define Is_host_pipe_frozen | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_PFREEZE_MASK)) |
tests if the current pipe is frozen
| #define Is_host_pipe_interrupt | ( | p | ) | (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_P0INT_MASK << (p))) |
tests if an interrupt is triggered by the selected pipe
| #define Is_host_pipe_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_P0INTE_MASK << (p))) |
tests if the selected pipe interrupt is enabled
| #define Is_host_read_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RWALL_MASK)) |
tests if pipe read allowed
| #define Is_host_resetting_pipe | ( | p | ) | (Tst_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PRST0_MASK << (p))) |
tests if the selected pipe is being reset
| #define Is_host_setup_ready | ( | ) | (Tst_bits(AVR32_USBB_upstax(P_CONTROL), AVR32_USBB_UPSTAX_TXSTPI_MASK)) |
tests if SETUP has been sent
Referenced by host_transfer_control().
| #define Is_host_setup_ready_interrupt_enabled | ( | ) | (Tst_bits(AVR32_USBB_upconx(P_CONTROL), AVR32_USBB_UPCONX_TXSTPE_MASK)) |
tests if SETUP pipe ready interrupt is enabled
| #define Is_host_setup_sent | ( | ) | (Is_host_fifocon(P_CONTROL)) |
tests if current bank sent for SETUP pipe
| #define Is_host_short_packet | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_SHORTPACKETI_MASK)) |
tests if SHORT PACKET received
| #define Is_host_short_packet_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_SHORTPACKETIE_MASK)) |
tests if SHORT PACKET received interrupt is enabled
| #define Is_host_stall | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RXSTALLDI_MASK)) |
tests if a STALL has been received
Referenced by host_get_data(), host_send_data(), and host_transfer_control().
| #define Is_host_stall_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RXSTALLDE_MASK)) |
tests if STALL received interrupt is enabled
| #define Is_host_timeout_error | ( | p | ) | (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_TIMEOUT_MASK)) |
| #define Is_host_underflow | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_TXSTPI_MASK)) |
tests if an underflow occurs
| #define Is_host_underflow_interrupt_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_TXSTPE_MASK)) |
tests if underflow interrupt is enabled
| #define Is_host_write_enabled | ( | p | ) | (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RWALL_MASK)) |
tests if pipe write allowed
1.8.5