Clock system configuration for clock example 1.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_DFLL0_DIV 1 |
#define | CONFIG_DFLL0_MUL 300 |
#define | CONFIG_DFLL0_SOURCE GENCLK_SRC_RCSYS |
#define | CONFIG_SYSCLK_CPU_DIV 2 |
#define | CONFIG_SYSCLK_PBA_DIV 2 |
#define | CONFIG_SYSCLK_PBB_DIV 2 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_DFLL |
#define CONFIG_DFLL0_DIV 1 |
Referenced by dfll_enable_config_defaults().
#define CONFIG_DFLL0_MUL 300 |
Referenced by dfll_enable_config_defaults().
#define CONFIG_DFLL0_SOURCE GENCLK_SRC_RCSYS |
Referenced by dfll_enable_config_defaults().
#define CONFIG_SYSCLK_CPU_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBA_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBB_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_DFLL |
Referenced by sysclk_init().