Chip-specific system clock manager configuration.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_HCACHE_ENABLE 1 |
#define | CONFIG_PLL0_DIV 4 |
#define | CONFIG_PLL0_MUL (180000000UL / BOARD_OSC0_HZ) |
#define | CONFIG_PLL0_SOURCE PLL_SRC_OSC0 |
#define | CONFIG_SYSCLK_CPU_DIV 0 |
#define | CONFIG_SYSCLK_PBA_DIV 0 |
#define | CONFIG_SYSCLK_PBB_DIV 0 |
#define | CONFIG_SYSCLK_PBC_DIV 0 |
#define | CONFIG_SYSCLK_PBD_DIV 0 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 |
#define CONFIG_HCACHE_ENABLE 1 |
#define CONFIG_PLL0_DIV 4 |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_MUL (180000000UL / BOARD_OSC0_HZ) |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0 |
Referenced by pll_enable_config_defaults().
#define CONFIG_SYSCLK_CPU_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBA_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBB_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBC_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBD_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 |
Referenced by sysclk_init().