Clock configuration.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_DFLL0_DIV 2 |
#define | CONFIG_DFLL0_MUL (80000000 / BOARD_OSC32_HZ) |
#define | CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC32K |
#define | CONFIG_SYSCLK_INIT_CPUMASK 0 |
#define | CONFIG_SYSCLK_INIT_HSBMASK 0 |
#define | CONFIG_SYSCLK_INIT_PBAMASK 0 |
#define | CONFIG_SYSCLK_INIT_PBBMASK 0 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_DFLL |
#define CONFIG_DFLL0_DIV 2 |
Referenced by dfll_enable_config_defaults().
#define CONFIG_DFLL0_MUL (80000000 / BOARD_OSC32_HZ) |
Referenced by dfll_enable_config_defaults().
#define CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC32K |
Referenced by dfll_enable_config_defaults().
#define CONFIG_SYSCLK_INIT_CPUMASK 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_INIT_HSBMASK 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_INIT_PBAMASK 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_INIT_PBBMASK 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_DFLL |
Referenced by sysclk_init().