nmasic.h File Reference

This module contains WILC ASIC specific internal APIs.

Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.

#include "../../common/include/nm_common.h"

Data Structures
struct	tstrM2mRev

Macros
#define	BOOTROM_REG   (0xc000c)
#define	BT_ACCEPTANCE_TIMER   0x700
#define	BT_ACPT_TIMER_THRE   0x000 /* Interrupt will be generated when rej/acc arb counter reach this value */
#define	BT_REG_TIMER_NULL_THRE   0x783 /* Threshold for generating NULL packet enabling wifi power-save mode */
#define	BT_REJ_ACPT_TIMER_TIME_BASE   4
#define	BT_REJECTION_TIMER   0x800
#define	COUNT_TO_ONE_US   39 /* Counts to generate 1 microsecond ticks from system clock */
#define	EFUSED_MAC(value)   (value & 0xffff0000)
#define	GET_CHIPID()   nmi_get_chipid()
#define	IRG_FLAGS_OFFSET   16
#define	ISNMC1000(id)   (((id & 0xfffff000) == 0x100000) ? 1 : 0)
#define	ISNMC1500(id)   (((id & 0xfffff000) == 0x150000) ? 1 : 0)
#define	M2M_FINISH_BOOT_ROM   0x10add09eUL
#define	M2M_FINISH_INIT_STATE   0x02532636UL
#define	M2M_START_FIRMWARE   0xef522f61UL
#define	M2M_START_PS_FIRMWARE   0x94992610UL
#define	M2M_WAIT_FOR_HOST_REG   (0x207bc)
#define	NMI_CHIPID   (NMI_PERIPH_REG_BASE)
#define	NMI_GP_REG_1   0x14a0
#define	NMI_PERIPH_REG_BASE   0x1000
#define	NMI_REV_REG   (0x207ac)
#define	NMI_STATE_REG   (0x108c)
#define	NMI_VMM_BASE   0x150000
#define	NMI_VMM_CORE_CFG   (NMI_VMM_BASE+0x14)
#define	PHY_MODE_11_MBPS   0x10141
#define	PHY_MODE_12_MBPS   0x10142
#define	PHY_MODE_18_MBPS   0x10142
#define	PHY_MODE_1_MBPS   0x10141
#define	PHY_MODE_24_MBPS   0x10142
#define	PHY_MODE_2_MBPS   0x10141
#define	PHY_MODE_36_MBPS   0x10142
#define	PHY_MODE_48_MBPS   0x10142
#define	PHY_MODE_54_MBPS   0x10142
#define	PHY_MODE_5_5_MBPS   0x10141
#define	PHY_MODE_6_MBPS   0x10142
#define	PHY_MODE_9_MBPS   0x10142
#define	PHY_MODE_MCS0_MBPS   0x10146
#define	PHY_MODE_MCS1_MBPS   0x10146
#define	PHY_MODE_MCS2_MBPS   0x10146
#define	PHY_MODE_MCS3_MBPS   0x10146
#define	PHY_MODE_MCS4_MBPS   0x10146
#define	PHY_MODE_MCS5_MBPS   0x10146
#define	PHY_MODE_MCS6_MBPS   0x10146
#define	PHY_MODE_MCS7_MBPS   0x10146
#define	rBT_CNT_INT   (WIFI_PERIPH_BASE+0x161E78)
#define	rBT_CNT_THR   (WIFI_PERIPH_BASE+0x161E28)
#define	rBT_SLOT_LUMP_CTL1   (WIFI_PERIPH_BASE+0x161E10)
#define	rBT_WIRE_SAMPLE_TIME   (WIFI_PERIPH_BASE+0x161E08)
#define	rCOE_AUTO_CTS_PKT   (WIFI_PERIPH_BASE+0x160470)
#define	rCOE_AUTO_PS_OFF_NULL_PKT   (WIFI_PERIPH_BASE+0x16046C)
#define	rCOE_AUTO_PS_ON_NULL_PKT   (WIFI_PERIPH_BASE+0x160468)
#define	rCOE_TOP_CTL   (WIFI_PERIPH_BASE+0x1124)
#define	rCOEXIST_CTL   (WIFI_PERIPH_BASE+0x161E00)
#define	rCOEXIST_TIMER   (WIFI_PERIPH_BASE+0x161E04)
#define	REV(id)   ( ((id) & 0x00000fff ) )
#define	REV_B0   (0x2B0)
#define	rNMI_GP_REG_0   (0x149c)
#define	rPA_CONTROL   (WIFI_PERIPH_BASE+0x9804)
#define	rTX_ABORT_NULL_FRM_DURATION_TIMEOUT_VALUE   (WIFI_PERIPH_BASE+0x16045C)
#define	rTX_ABORT_NULL_FRM_PHY_TX_MODE_SETTING   (WIFI_PERIPH_BASE+0x160464)
#define	rTX_ABORT_NULL_FRM_RATE_POWER_LEVEL   (WIFI_PERIPH_BASE+0x160460)
#define	TX_RATE_11_MBPS   0x3
#define	TX_RATE_12_MBPS   0xa
#define	TX_RATE_18_MBPS   0xe
#define	TX_RATE_1_MBPS   0x0
#define	TX_RATE_24_MBPS   0x9
#define	TX_RATE_2_MBPS   0x1
#define	TX_RATE_36_MBPS   0xd
#define	TX_RATE_48_MBPS   0x8
#define	TX_RATE_54_MBPS   0xc
#define	TX_RATE_5_5_MBPS   0x2
#define	TX_RATE_6_MBPS   0xb
#define	TX_RATE_9_MBPS   0xf
#define	TX_RATE_MCS0_MBPS   0x80
#define	TX_RATE_MCS1_MBPS   0x81
#define	TX_RATE_MCS2_MBPS   0x82
#define	TX_RATE_MCS3_MBPS   0x83
#define	TX_RATE_MCS4_MBPS   0x84
#define	TX_RATE_MCS5_MBPS   0x85
#define	TX_RATE_MCS6_MBPS   0x86
#define	TX_RATE_MCS7_MBPS   0x87
#define	WIFI_PERIPH_BASE   0x00000000
#define	WILC_CLK_STATUS_BIT   NBIT2
#define	WILC_CLK_STATUS_REG   0x13
#define	WILC_FROM_INTERFACE_TO_WF_BIT   NBIT0
#define	WILC_FROM_INTERFACE_TO_WF_REG   0x0E
#define	WILC_INT_CLEAR_REG   0x44
#define	WILC_INT_STATUS_REG   0x40
#define	WILC_TO_INTERFACE_FROM_WF_BIT   NBIT0
#define	WILC_TO_INTERFACE_FROM_WF_REG   0x14
#define	WILC_WAKEUP_BIT   NBIT1
#define	WILC_WAKEUP_REG   0x1

Functions
sint8	chip_deinit (void)
void	chip_idle (void)
sint8	chip_reset (void)
sint8	chip_reset_and_cpu_halt (void)
sint8	chip_sleep (void)
sint8	chip_wake (void)
sint8	cpu_start (void)
sint8	cpu_start_bt (void)
sint8	enable_interrupts (void)
sint8	firmware_download (void)
sint8	firmware_download_bt (void)
sint8	get_gpio_val (uint8 gpio, uint8 *val)
sint8	is_valid_gpio (uint8 gpio)
uint32	nmi_get_chipid (void)
sint8	nmi_get_mac_address (uint8 *pu8MacAddr)
sint8	nmi_get_otp_mac_address (uint8 *pu8MacAddr, uint8 *pu8IsValid)
uint32	nmi_get_rfrevid (void)
void	nmi_set_sys_clk_src_to_xo (void)
void	nmi_update_pll (void)
sint8	pullup_ctrl (uint32 pinmask, uint8 enable)
void	restore_pmu_settings_after_global_reset (void)
sint8	set_gpio_dir (uint8 gpio, uint8 dir)
sint8	set_gpio_val (uint8 gpio, uint8 val)
sint8	wait_for_bootrom (void)
sint8	wait_for_firmware_start (void)

#define BOOTROM_REG   (0xc000c)

#define BT_ACCEPTANCE_TIMER   0x700

#define BT_ACPT_TIMER_THRE   0x000 /* Interrupt will be generated when rej/acc arb counter reach this value */

#define BT_REG_TIMER_NULL_THRE   0x783 /* Threshold for generating NULL packet enabling wifi power-save mode */

#define BT_REJ_ACPT_TIMER_TIME_BASE   4

#define BT_REJECTION_TIMER   0x800

#define COUNT_TO_ONE_US   39 /* Counts to generate 1 microsecond ticks from system clock */

#define EFUSED_MAC

(

value

)

(value & 0xffff0000)

Referenced by nmi_get_otp_mac_address().

#define GET_CHIPID

(

)

nmi_get_chipid()

#define IRG_FLAGS_OFFSET   16

Referenced by hif_isr().

#define ISNMC1000

(

id

)

(((id & 0xfffff000) == 0x100000) ? 1 : 0)

#define ISNMC1500

(

id

)

(((id & 0xfffff000) == 0x150000) ? 1 : 0)

#define M2M_FINISH_BOOT_ROM   0x10add09eUL

#define M2M_FINISH_INIT_STATE   0x02532636UL

Referenced by wait_for_firmware_start().

#define M2M_START_FIRMWARE   0xef522f61UL

#define M2M_START_PS_FIRMWARE   0x94992610UL

#define M2M_WAIT_FOR_HOST_REG   (0x207bc)

#define NMI_CHIPID   (NMI_PERIPH_REG_BASE)

#define NMI_GP_REG_1   0x14a0

#define NMI_PERIPH_REG_BASE   0x1000

#define NMI_REV_REG   (0x207ac)

Referenced by cpu_start(), and nm_get_firmware_info().

#define NMI_STATE_REG   (0x108c)

Referenced by cpu_start(), and wait_for_firmware_start().

#define NMI_VMM_BASE   0x150000

#define NMI_VMM_CORE_CFG   (NMI_VMM_BASE+0x14)

Referenced by cpu_start().

#define PHY_MODE_11_MBPS   0x10141

#define PHY_MODE_12_MBPS   0x10142

#define PHY_MODE_18_MBPS   0x10142

#define PHY_MODE_1_MBPS   0x10141

#define PHY_MODE_24_MBPS   0x10142

#define PHY_MODE_2_MBPS   0x10141

#define PHY_MODE_36_MBPS   0x10142

#define PHY_MODE_48_MBPS   0x10142

#define PHY_MODE_54_MBPS   0x10142

#define PHY_MODE_5_5_MBPS   0x10141

#define PHY_MODE_6_MBPS   0x10142

#define PHY_MODE_9_MBPS   0x10142

#define PHY_MODE_MCS0_MBPS   0x10146

#define PHY_MODE_MCS1_MBPS   0x10146

#define PHY_MODE_MCS2_MBPS   0x10146

#define PHY_MODE_MCS3_MBPS   0x10146

#define PHY_MODE_MCS4_MBPS   0x10146

#define PHY_MODE_MCS5_MBPS   0x10146

#define PHY_MODE_MCS6_MBPS   0x10146

#define PHY_MODE_MCS7_MBPS   0x10146

#define rBT_CNT_INT   (WIFI_PERIPH_BASE+0x161E78)

#define rBT_CNT_THR   (WIFI_PERIPH_BASE+0x161E28)

#define rBT_SLOT_LUMP_CTL1   (WIFI_PERIPH_BASE+0x161E10)

#define rBT_WIRE_SAMPLE_TIME   (WIFI_PERIPH_BASE+0x161E08)

#define rCOE_AUTO_CTS_PKT   (WIFI_PERIPH_BASE+0x160470)

#define rCOE_AUTO_PS_OFF_NULL_PKT   (WIFI_PERIPH_BASE+0x16046C)

#define rCOE_AUTO_PS_ON_NULL_PKT   (WIFI_PERIPH_BASE+0x160468)

#define rCOE_TOP_CTL   (WIFI_PERIPH_BASE+0x1124)

#define rCOEXIST_CTL   (WIFI_PERIPH_BASE+0x161E00)

#define rCOEXIST_TIMER   (WIFI_PERIPH_BASE+0x161E04)

#define REV

(

id

)

( ((id) & 0x00000fff ) )

#define REV_B0   (0x2B0)

#define rNMI_GP_REG_0   (0x149c)

Referenced by nmi_get_mac_address(), and nmi_get_otp_mac_address().

#define rPA_CONTROL   (WIFI_PERIPH_BASE+0x9804)

#define rTX_ABORT_NULL_FRM_DURATION_TIMEOUT_VALUE   (WIFI_PERIPH_BASE+0x16045C)

#define rTX_ABORT_NULL_FRM_PHY_TX_MODE_SETTING   (WIFI_PERIPH_BASE+0x160464)

#define rTX_ABORT_NULL_FRM_RATE_POWER_LEVEL   (WIFI_PERIPH_BASE+0x160460)

#define TX_RATE_11_MBPS   0x3

#define TX_RATE_12_MBPS   0xa

#define TX_RATE_18_MBPS   0xe

#define TX_RATE_1_MBPS   0x0

#define TX_RATE_24_MBPS   0x9

#define TX_RATE_2_MBPS   0x1

#define TX_RATE_36_MBPS   0xd

#define TX_RATE_48_MBPS   0x8

#define TX_RATE_54_MBPS   0xc

#define TX_RATE_5_5_MBPS   0x2

#define TX_RATE_6_MBPS   0xb

#define TX_RATE_9_MBPS   0xf

#define TX_RATE_MCS0_MBPS   0x80

#define TX_RATE_MCS1_MBPS   0x81

#define TX_RATE_MCS2_MBPS   0x82

#define TX_RATE_MCS3_MBPS   0x83

#define TX_RATE_MCS4_MBPS   0x84

#define TX_RATE_MCS5_MBPS   0x85

#define TX_RATE_MCS6_MBPS   0x86

#define TX_RATE_MCS7_MBPS   0x87

#define WIFI_PERIPH_BASE   0x00000000

#define WILC_CLK_STATUS_BIT   NBIT2

Referenced by chip_wake().

#define WILC_CLK_STATUS_REG   0x13

Referenced by chip_wake().

#define WILC_FROM_INTERFACE_TO_WF_BIT   NBIT0

Referenced by chip_sleep(), and chip_wake().

#define WILC_FROM_INTERFACE_TO_WF_REG   0x0E

Referenced by chip_sleep(), and chip_wake().

#define WILC_INT_CLEAR_REG   0x44

Referenced by hif_isr().

#define WILC_INT_STATUS_REG   0x40

Referenced by hif_isr().

#define WILC_TO_INTERFACE_FROM_WF_BIT   NBIT0

Referenced by chip_sleep().

#define WILC_TO_INTERFACE_FROM_WF_REG   0x14

Referenced by chip_sleep().

#define WILC_WAKEUP_BIT   NBIT1

Referenced by chip_idle(), chip_sleep(), and chip_wake().

#define WILC_WAKEUP_REG   0x1

Referenced by chip_idle(), chip_sleep(), and chip_wake().

sint8 chip_deinit

(

void

)

stop the firmware, need a re-download

References M2M_DBG, M2M_ERR, M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), NMI_GLB_RESET_0, and timeout.

Referenced by nm_drv_deinit().

void chip_idle

(

void

)

References nm_read_reg_with_ret(), nm_write_reg(), WILC_WAKEUP_BIT, and WILC_WAKEUP_REG.

sint8 chip_reset

(

void

)

References M2M_SUCCESS, nm_bsp_sleep(), nm_write_reg(), NMI_GLB_RESET_0, NMI_GLB_RESET_1, nmi_set_sys_clk_src_to_xo(), and restore_pmu_settings_after_global_reset().

sint8 chip_reset_and_cpu_halt

(

void

)

sint8 chip_sleep

(

void

)

References M2M_ERR, M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), WILC_FROM_INTERFACE_TO_WF_BIT, WILC_FROM_INTERFACE_TO_WF_REG, WILC_TO_INTERFACE_FROM_WF_BIT, WILC_TO_INTERFACE_FROM_WF_REG, WILC_WAKEUP_BIT, and WILC_WAKEUP_REG.

Referenced by hif_chip_sleep().

sint8 chip_wake

(

void

)

References M2M_ERR, M2M_ERR_TIME_OUT, M2M_SUCCESS, nm_bus_reset(), nm_read_reg_with_ret(), nm_write_reg(), WAKUP_TRAILS_TIMEOUT, WILC_CLK_STATUS_BIT, WILC_CLK_STATUS_REG, WILC_FROM_INTERFACE_TO_WF_BIT, WILC_FROM_INTERFACE_TO_WF_REG, WILC_WAKEUP_BIT, and WILC_WAKEUP_REG.

Referenced by hif_chip_wake().

sint8 cpu_start

(

void

)

reset regs

Go...

References M2M_ERR, M2M_ERR_BUS_FAIL, M2M_SUCCESS, nm_bsp_sleep(), nm_read_reg_with_ret(), nm_write_reg(), NMI_GLB_RESET_0, NMI_REV_REG, NMI_STATE_REG, and NMI_VMM_CORE_CFG.

Referenced by nm_drv_init().

sint8 cpu_start_bt

(

void

)

Go...

References M2M_SUCCESS, nm_bsp_sleep(), nm_read_reg_with_ret(), and nm_write_reg().

Referenced by nm_drv_init().

sint8 enable_interrupts

(

void

)

interrupt pin mux select

interrupt enable

References M2M_ERR_BUS_FAIL, M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), NMI_INTR_ENABLE, and NMI_PIN_MUX_0.

Referenced by nm_drv_init().

sint8 firmware_download

(

void

)

References M2M_DBG, m2m_memcpy(), M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_block(), and nm_write_reg().

Referenced by nm_drv_init().

sint8 firmware_download_bt

(

void

)

References firmware_ble, M2M_DBG, m2m_memcpy(), nm_read_reg_with_ret(), nm_write_block(), and nm_write_reg().

Referenced by nm_drv_init().

sint8 get_gpio_val	(	uint8	gpio,
		uint8 *	val
	)

References M2M_SUCCESS, and nm_read_reg_with_ret().

Referenced by gpio_ioctl().

sint8 is_valid_gpio

(

uint8

gpio

)

Referenced by m2m_wifi_set_antenna_mode().

uint32 nmi_get_chipid

(

void

)

References M2M_SUCCESS, and nm_read_reg_with_ret().

Referenced by nm_drv_init(), and nm_get_firmware_info().

sint8 nmi_get_mac_address

(

uint8 *

pu8MacAddr

)

References M2M_SUCCESS, nm_read_block(), nm_read_reg_with_ret(), and rNMI_GP_REG_0.

Referenced by m2m_wifi_get_mac_address().

sint8 nmi_get_otp_mac_address	(	uint8 *	pu8MacAddr,
		uint8 *	pu8IsValid
	)

References EFUSED_MAC, M2M_DBG, m2m_memset(), M2M_SUCCESS, nm_read_block(), nm_read_reg_with_ret(), and rNMI_GP_REG_0.

Referenced by m2m_wifi_get_otp_mac_address().

uint32 nmi_get_rfrevid

(

void

)

References M2M_SUCCESS, and nm_read_reg_with_ret().

void nmi_set_sys_clk_src_to_xo

(

void

)

References nm_read_reg(), nm_write_reg(), and nmi_update_pll().

Referenced by chip_reset().

void nmi_update_pll

(

void

)

References nm_read_reg(), and nm_write_reg().

Referenced by nmi_set_sys_clk_src_to_xo().

sint8 pullup_ctrl	(	uint32	pinmask,
		uint8	enable
	)

References M2M_ERR, M2M_SUCCESS, nm_read_reg_with_ret(), and nm_write_reg().

Referenced by m2m_periph_pullup_ctrl().

void restore_pmu_settings_after_global_reset

(

void

)

References nm_write_reg().

Referenced by chip_reset().

sint8 set_gpio_dir	(	uint8	gpio,
		uint8	dir
	)

References M2M_SUCCESS, nm_read_reg_with_ret(), and nm_write_reg().

Referenced by gpio_ioctl().

sint8 set_gpio_val	(	uint8	gpio,
		uint8	val
	)

References M2M_SUCCESS, nm_read_reg_with_ret(), and nm_write_reg().

Referenced by gpio_ioctl().

sint8 wait_for_bootrom

(

void

)

Referenced by nm_drv_init().

sint8 wait_for_firmware_start

(

void

)

References M2M_DBG, M2M_ERR_INIT, M2M_FINISH_INIT_STATE, M2M_SUCCESS, nm_bsp_sleep(), nm_read_reg(), nm_write_reg(), NMI_STATE_REG, and TIMEOUT.

Referenced by nm_drv_init().