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This module contains WINC3400 SPI protocol bus APIs implementation.

Copyright (c) 2017-2021 Microchip Technology Inc. and its subsidiaries.

#include "common/include/nm_common.h"
#include "bus_wrapper/include/nm_bus_wrapper.h"
#include "nmspi.h"

Macros
#define	CMD_DMA_EXT_READ 0xc8

#define	CMD_DMA_EXT_WRITE 0xc7

#define	CMD_INTERNAL_READ 0xc4

#define	CMD_INTERNAL_WRITE 0xc3

#define	CMD_RESET 0xcf

#define	CMD_SINGLE_READ 0xca

#define	CMD_SINGLE_WRITE 0xc9

#define	DATA_PKT_SZ DATA_PKT_SZ_8K

#define	DATA_PKT_SZ_1K 1024

#define	DATA_PKT_SZ_256 256

#define	DATA_PKT_SZ_4K (4 * 1024)

#define	DATA_PKT_SZ_512 512

#define	DATA_PKT_SZ_8K (8 * 1024)

#define	N_FAIL -1

#define	N_OK 0

#define	N_RESET -2

#define	N_RETRY -3

#define	NMI_CHIPID (NMI_PERIPH_REG_BASE)

#define	NMI_INTR_ENABLE (NMI_INTR_REG_BASE)

#define	NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE+0xa00)

#define	NMI_PERIPH_REG_BASE 0x1000

#define	NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408)

#define	NMI_SPI_CTL (NMI_SPI_REG_BASE)

#define	NMI_SPI_INTR_CTL (NMI_SPI_REG_BASE+0x2c)

#define	NMI_SPI_MASTER_DMA_ADDR (NMI_SPI_REG_BASE+0x4)

#define	NMI_SPI_MASTER_DMA_COUNT (NMI_SPI_REG_BASE+0x8)

#define	NMI_SPI_PROTOCOL_CONFIG (NMI_SPI_REG_BASE+0x24)

#define	NMI_SPI_PROTOCOL_OFFSET (NMI_SPI_PROTOCOL_CONFIG-NMI_SPI_REG_BASE)

#define	NMI_SPI_REG_BASE 0xe800

#define	NMI_SPI_SLAVE_DMA_ADDR (NMI_SPI_REG_BASE+0xc)

#define	NMI_SPI_SLAVE_DMA_COUNT (NMI_SPI_REG_BASE+0x10)

#define	NMI_SPI_TX_MODE (NMI_SPI_REG_BASE+0x20)

#define	SPI_BASE NMI_SPI_REG_BASE

#define	SPI_RESP_RETRY_COUNT (10)

#define	SPI_RETRY_COUNT (10)

Functions
static uint8	crc7 (uint8 crc, const uint8 *buffer, uint32 len)

static uint8	crc7_byte (uint8 crc, uint8 data)

sint8	nm_spi_deinit (void)
	DeInitialize the SPI. More...

sint8	nm_spi_init (void)
	Initialize the SPI. More...

sint8	nm_spi_read_block (uint32 addr, uint8 *buf, uint16 size)

uint32	nm_spi_read_reg (uint32 u32Addr)

sint8	nm_spi_read_reg_with_ret (uint32 addr, uint32 *u32data)

sint8	nm_spi_reset (void)
	Reset the SPI. More...

sint8	nm_spi_write_block (uint32 addr, uint8 *buf, uint16 size)

sint8	nm_spi_write_reg (uint32 addr, uint32 u32data)

static sint8	nmi_spi_read (uint8 *b, uint16 sz)

static sint8	nmi_spi_write (uint8 *b, uint16 sz)

static sint8	nmi_spi_writeread (uint8 bw, uint8 br, uint16 sz)

static sint8	spi_cmd (uint8 cmd, uint32 adr, uint32 u32data, uint32 sz, uint8 clockless)

static sint8	spi_cmd_rsp (uint8 cmd)

static sint8	spi_data_read (uint8 *b, uint16 sz, uint8 clockless)

static sint8	spi_data_rsp (uint8 cmd)

static sint8	spi_data_write (uint8 *b, uint16 sz)

static void	spi_init_pkt_sz (void)

Variables
static const uint8	crc7_syndrome_table [256]

static uint8	gu8Crc_off = 0

#define CMD_DMA_EXT_READ 0xc8

Referenced by nm_spi_read_block(), and spi_cmd().

#define CMD_DMA_EXT_WRITE 0xc7

Referenced by nm_spi_write_block(), and spi_cmd().

#define CMD_INTERNAL_READ 0xc4

Referenced by nm_spi_read_reg_with_ret(), and spi_cmd().

#define CMD_INTERNAL_WRITE 0xc3

Referenced by nm_spi_write_reg(), and spi_cmd().

#define CMD_RESET 0xcf

Referenced by nm_spi_read_block(), nm_spi_read_reg_with_ret(), nm_spi_reset(), nm_spi_write_block(), nm_spi_write_reg(), and spi_cmd().

#define CMD_SINGLE_READ 0xca

Referenced by nm_spi_read_reg_with_ret(), and spi_cmd().

#define CMD_SINGLE_WRITE 0xc9

Referenced by nm_spi_write_reg(), and spi_cmd().

#define DATA_PKT_SZ DATA_PKT_SZ_8K

Referenced by spi_data_read(), spi_data_write(), and spi_init_pkt_sz().

#define DATA_PKT_SZ_1K 1024

#define DATA_PKT_SZ_256 256

#define DATA_PKT_SZ_4K (4 * 1024)

#define DATA_PKT_SZ_512 512

#define DATA_PKT_SZ_8K (8 * 1024)

#define N_FAIL -1

Referenced by nm_spi_read_block(), nm_spi_read_reg_with_ret(), nm_spi_reset(), nm_spi_write_block(), nm_spi_write_reg(), spi_cmd(), spi_cmd_rsp(), spi_data_read(), spi_data_rsp(), and spi_data_write().

#define N_OK 0

Referenced by nm_spi_read_block(), nm_spi_read_reg_with_ret(), nm_spi_reset(), nm_spi_write_block(), nm_spi_write_reg(), spi_cmd(), spi_cmd_rsp(), spi_data_read(), spi_data_rsp(), and spi_data_write().

#define N_RESET -2

#define N_RETRY -3

#define NMI_CHIPID (NMI_PERIPH_REG_BASE)

#define NMI_INTR_ENABLE (NMI_INTR_REG_BASE)

#define NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE+0xa00)

#define NMI_PERIPH_REG_BASE 0x1000

#define NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408)

#define NMI_SPI_CTL (NMI_SPI_REG_BASE)

#define NMI_SPI_INTR_CTL (NMI_SPI_REG_BASE+0x2c)

#define NMI_SPI_MASTER_DMA_ADDR (NMI_SPI_REG_BASE+0x4)

#define NMI_SPI_MASTER_DMA_COUNT (NMI_SPI_REG_BASE+0x8)

#define NMI_SPI_PROTOCOL_CONFIG (NMI_SPI_REG_BASE+0x24)

Referenced by nm_spi_init().

#define NMI_SPI_PROTOCOL_OFFSET (NMI_SPI_PROTOCOL_CONFIG-NMI_SPI_REG_BASE)

#define NMI_SPI_REG_BASE 0xe800

#define NMI_SPI_SLAVE_DMA_ADDR (NMI_SPI_REG_BASE+0xc)

#define NMI_SPI_SLAVE_DMA_COUNT (NMI_SPI_REG_BASE+0x10)

#define NMI_SPI_TX_MODE (NMI_SPI_REG_BASE+0x20)

#define SPI_BASE NMI_SPI_REG_BASE

Referenced by spi_init_pkt_sz().

#define SPI_RESP_RETRY_COUNT (10)

#define SPI_RETRY_COUNT (10)

Referenced by nm_spi_read_block(), nm_spi_read_reg_with_ret(), nm_spi_write_block(), and nm_spi_write_reg().

static uint8 crc7	(	uint8	crc,
		const uint8 *	buffer,
		uint32	len
	)

inlinestatic

References crc7_byte().

Referenced by spi_cmd().

static uint8 crc7_byte	(	uint8	crc,
		uint8	data
	)

inlinestatic

References crc7_syndrome_table.

Referenced by crc7().

nm_spi_deinit ( void )

DeInitialize the SPI.

Returns: M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure

References gu8Crc_off, and M2M_SUCCESS.

Referenced by nm_drv_deinit(), and nm_drv_init_start().

nm_spi_init ( void )

Initialize the SPI.

DeInitialize the SPI.

Returns: M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure

configure protocol

make sure can read back chip id correctly

References gu8Crc_off, M2M_DBG, M2M_ERR, M2M_ERR_BUS_FAIL, M2M_SUCCESS, nm_spi_read_reg_with_ret(), nm_spi_write_reg(), NMI_SPI_PROTOCOL_CONFIG, and spi_init_pkt_sz().

Referenced by nm_drv_init_download_mode(), and nm_drv_init_hold().

sint8 nm_spi_read_block	(	uint32	addr,
		uint8 *	buf,
		uint16	size
	)

Command

Data

References CMD_DMA_EXT_READ, CMD_RESET, M2M_ERR, N_FAIL, N_OK, nm_bsp_sleep(), spi_cmd(), spi_cmd_rsp(), spi_data_read(), and SPI_RETRY_COUNT.

Referenced by p_nm_read_block().

uint32 nm_spi_read_reg ( uint32 u32Addr )

References nm_spi_read_reg_with_ret().

Referenced by nm_read_reg(), and spi_init_pkt_sz().

sint8 nm_spi_read_reg_with_ret	(	uint32	addr,
		uint32 *	u32data
	)

NMC1000 clockless registers.

References CMD_INTERNAL_READ, CMD_RESET, CMD_SINGLE_READ, M2M_ERR, N_FAIL, N_OK, nm_bsp_sleep(), spi_cmd(), spi_cmd_rsp(), spi_data_read(), and SPI_RETRY_COUNT.

Referenced by nm_read_reg_with_ret(), nm_spi_init(), and nm_spi_read_reg().

nm_spi_reset ( void )

Reset the SPI.

Returns: M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure

References CMD_RESET, M2M_ERR, M2M_INFO, N_FAIL, N_OK, nmi_spi_writeread(), spi_cmd(), and spi_cmd_rsp().

Referenced by nm_bus_reset().

sint8 nm_spi_write_block	(	uint32	addr,
		uint8 *	buf,
		uint16	size
	)

Command

Data

Data RESP

References CMD_DMA_EXT_WRITE, CMD_RESET, M2M_ERR, N_FAIL, N_OK, nm_bsp_sleep(), spi_cmd(), spi_cmd_rsp(), spi_data_rsp(), spi_data_write(), and SPI_RETRY_COUNT.

Referenced by p_nm_write_block().

sint8 nm_spi_write_reg	(	uint32	addr,
		uint32	u32data
	)

NMC1000 clockless registers.

References CMD_INTERNAL_WRITE, CMD_RESET, CMD_SINGLE_WRITE, M2M_ERR, N_FAIL, N_OK, nm_bsp_sleep(), spi_cmd(), spi_cmd_rsp(), and SPI_RETRY_COUNT.

Referenced by nm_spi_init(), nm_write_reg(), and spi_init_pkt_sz().

static sint8 nmi_spi_read	(	uint8 *	b,
		uint16	sz
	)

inlinestatic

References nm_spi_rw(), and NULL.

Referenced by spi_cmd_rsp(), spi_data_read(), and spi_data_rsp().

static sint8 nmi_spi_write	(	uint8 *	b,
		uint16	sz
	)

inlinestatic

References nm_spi_rw(), and NULL.

Referenced by spi_cmd(), and spi_data_write().

static sint8 nmi_spi_writeread	(	uint8 *	bw,
		uint8 *	br,
		uint16	sz
	)

static

References nm_spi_rw().

Referenced by nm_spi_reset().

static sint8 spi_cmd	(	uint8	cmd,
		uint32	adr,
		uint32	u32data,
		uint32	sz,
		uint8	clockless
	)

static

References CMD_DMA_EXT_READ, CMD_DMA_EXT_WRITE, CMD_INTERNAL_READ, CMD_INTERNAL_WRITE, CMD_RESET, CMD_SINGLE_READ, CMD_SINGLE_WRITE, crc7(), gu8Crc_off, M2M_ERR, M2M_SUCCESS, N_FAIL, N_OK, and nmi_spi_write().

Referenced by nm_spi_read_block(), nm_spi_read_reg_with_ret(), nm_spi_reset(), nm_spi_write_block(), and nm_spi_write_reg().

static sint8 spi_cmd_rsp ( uint8 cmd )

static

Command/Control response

State response

References M2M_ERR, M2M_SUCCESS, N_FAIL, N_OK, and nmi_spi_read().

Referenced by nm_spi_read_block(), nm_spi_read_reg_with_ret(), nm_spi_reset(), nm_spi_write_block(), and nm_spi_write_reg().

static sint8 spi_data_read	(	uint8 *	b,
		uint16	sz,
		uint8	clockless
	)

static

Data

Data Response header

Read bytes

Read Crc

References DATA_PKT_SZ, gu8Crc_off, M2M_ERR, M2M_SUCCESS, N_FAIL, N_OK, and nmi_spi_read().

Referenced by nm_spi_read_block(), and nm_spi_read_reg_with_ret().

static sint8 spi_data_rsp ( uint8 cmd )

static

References gu8Crc_off, M2M_ERR, M2M_SUCCESS, N_FAIL, N_OK, and nmi_spi_read().

Referenced by nm_spi_write_block().

static sint8 spi_data_write	(	uint8 *	b,
		uint16	sz
	)

static

Data

Write command

Write data

Write Crc

References DATA_PKT_SZ, gu8Crc_off, M2M_ERR, M2M_SUCCESS, N_FAIL, N_OK, and nmi_spi_write().

Referenced by nm_spi_write_block().

static void spi_init_pkt_sz ( void )

static

References DATA_PKT_SZ, nm_spi_read_reg(), nm_spi_write_reg(), and SPI_BASE.

Referenced by nm_spi_init().

const uint8 crc7_syndrome_table[256]

static

Referenced by crc7_byte().

uint8 gu8Crc_off = 0

static

Referenced by nm_spi_deinit(), nm_spi_init(), spi_cmd(), spi_data_read(), spi_data_rsp(), and spi_data_write().