SPI Flash.
Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
#include "spi_flash/include/spi_flash.h"
Macros | |
#define | CORTUS_SHARE_MEM_BASE (0x60000000UL) |
#define | DUMMY_REGISTER (0x1084) |
#define | FLASH_MULTI_WRITE |
#define | GET_UINT32(X, Y) (X[0+Y] + ((uint32)X[1+Y]<<8) + ((uint32)X[2+Y]<<16) +((uint32)X[3+Y]<<24)) |
#define | HOST_SHARE_MEM_BASE (0xd0000UL) |
#define | MAX_ATTEMPT_STATUS_READ 50000 |
#define | MAX_PROG_CNT 2 |
#define | MAX_RETRY 4 |
#define | NMI_SPI_FLASH_ADDR (0x111c) |
#define | SPI_FLASH_BASE (0x10200) |
#define | SPI_FLASH_BUF1 (SPI_FLASH_BASE + 0x0c) |
#define | SPI_FLASH_BUF2 (SPI_FLASH_BASE + 0x10) |
#define | SPI_FLASH_BUF_DIR (SPI_FLASH_BASE + 0x14) |
#define | SPI_FLASH_CMD_CNT (SPI_FLASH_BASE + 0x04) |
#define | SPI_FLASH_DATA_CNT (SPI_FLASH_BASE + 0x08) |
#define | SPI_FLASH_DMA_ADDR (SPI_FLASH_BASE + 0x1c) |
#define | SPI_FLASH_MODE (SPI_FLASH_BASE + 0x00) |
#define | SPI_FLASH_MSB_CTL (SPI_FLASH_BASE + 0x20) |
#define | SPI_FLASH_TR_DONE (SPI_FLASH_BASE + 0x18) |
#define | SPI_FLASH_TX_CTL (SPI_FLASH_BASE + 0x24) |
#define | TIMEOUT (-1) /*MS*/ |
Functions | |
sint8 | spi_flash_erase (uint32 u32Offset, uint32 u32Sz) |
Erase a specified portion of SPI Flash. . More... | |
uint32 | spi_flash_get_size (void) |
Get size of SPI Flash. More... | |
static sint8 | spi_flash_load_to_cortus_mem (uint32 u32MemAdr, uint32 u32FlashAdr, uint32 u32Sz) |
static sint8 | spi_flash_page_program (uint32 u32MemAdr, uint32 u32FlashAdr, uint32 u32Sz) |
static sint8 | spi_flash_pp (uint32 u32Offset, uint8 *pu8Buf, uint16 u16Sz) |
static uint32 | spi_flash_rdid (void) |
Read SPI Flash ID. More... | |
sint8 | spi_flash_read (uint8 *pu8Buf, uint32 u32offset, uint32 u32Sz) |
Read a specified portion of data from SPI Flash. . More... | |
static sint8 | spi_flash_read_internal (uint8 *pu8Buf, uint32 u32Addr, uint32 u32Sz) |
static sint8 | spi_flash_read_status_reg (uint8 *val) |
static sint8 | spi_flash_sector_erase (uint32 u32FlashAdr) |
sint8 | spi_flash_write (uint8 *pu8Buf, uint32 u32Offset, uint32 u32Sz) |
Write a specified portion of data to SPI Flash. . More... | |
static sint8 | spi_flash_write_disable (void) |
Send write disable command to SPI flash. More... | |
static sint8 | spi_flash_write_enable (void) |
Send write enable command to SPI flash. More... | |
#define CORTUS_SHARE_MEM_BASE (0x60000000UL) |
#define DUMMY_REGISTER (0x1084) |
Referenced by spi_flash_rdid(), and spi_flash_read_status_reg().
#define FLASH_MULTI_WRITE |
#define GET_UINT32 | ( | X, | |
Y | |||
) | (X[0+Y] + ((uint32)X[1+Y]<<8) + ((uint32)X[2+Y]<<16) +((uint32)X[3+Y]<<24)) |
#define HOST_SHARE_MEM_BASE (0xd0000UL) |
Referenced by spi_flash_pp(), and spi_flash_read_internal().
#define MAX_ATTEMPT_STATUS_READ 50000 |
Referenced by spi_flash_erase(), and spi_flash_pp().
#define MAX_PROG_CNT 2 |
Referenced by spi_flash_erase(), and spi_flash_pp().
#define MAX_RETRY 4 |
Referenced by spi_flash_erase(), and spi_flash_pp().
#define NMI_SPI_FLASH_ADDR (0x111c) |
#define SPI_FLASH_BASE (0x10200) |
#define SPI_FLASH_BUF1 (SPI_FLASH_BASE + 0x0c) |
#define SPI_FLASH_BUF2 (SPI_FLASH_BASE + 0x10) |
Referenced by spi_flash_load_to_cortus_mem().
#define SPI_FLASH_BUF_DIR (SPI_FLASH_BASE + 0x14) |
#define SPI_FLASH_CMD_CNT (SPI_FLASH_BASE + 0x04) |
#define SPI_FLASH_DATA_CNT (SPI_FLASH_BASE + 0x08) |
#define SPI_FLASH_DMA_ADDR (SPI_FLASH_BASE + 0x1c) |
#define SPI_FLASH_MODE (SPI_FLASH_BASE + 0x00) |
#define SPI_FLASH_MSB_CTL (SPI_FLASH_BASE + 0x20) |
#define SPI_FLASH_TR_DONE (SPI_FLASH_BASE + 0x18) |
#define SPI_FLASH_TX_CTL (SPI_FLASH_BASE + 0x24) |
#define TIMEOUT (-1) /*MS*/ |
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References M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), SPI_FLASH_BUF1, SPI_FLASH_BUF2, SPI_FLASH_BUF_DIR, SPI_FLASH_CMD_CNT, SPI_FLASH_DATA_CNT, SPI_FLASH_DMA_ADDR, and SPI_FLASH_TR_DONE.
Referenced by spi_flash_read_internal().
References M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), SPI_FLASH_BUF1, SPI_FLASH_BUF_DIR, SPI_FLASH_CMD_CNT, SPI_FLASH_DATA_CNT, SPI_FLASH_DMA_ADDR, and SPI_FLASH_TR_DONE.
Referenced by spi_flash_pp().
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Read SPI Flash ID.
References DUMMY_REGISTER, M2M_ERR_INIT, M2M_PRINT, M2M_SUCCESS, nm_read_reg(), nm_read_reg_with_ret(), nm_write_reg(), SPI_FLASH_BUF1, SPI_FLASH_BUF_DIR, SPI_FLASH_CMD_CNT, SPI_FLASH_DATA_CNT, SPI_FLASH_DMA_ADDR, and SPI_FLASH_TR_DONE.
Referenced by spi_flash_get_size().
References HOST_SHARE_MEM_BASE, M2M_SUCCESS, nm_read_block(), and spi_flash_load_to_cortus_mem().
Referenced by spi_flash_read().
References DUMMY_REGISTER, M2M_SUCCESS, nm_read_reg(), nm_read_reg_with_ret(), nm_write_reg(), SPI_FLASH_BUF1, SPI_FLASH_BUF_DIR, SPI_FLASH_CMD_CNT, SPI_FLASH_DATA_CNT, SPI_FLASH_DMA_ADDR, and SPI_FLASH_TR_DONE.
Referenced by spi_flash_erase(), and spi_flash_pp().
References M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), SPI_FLASH_BUF1, SPI_FLASH_BUF_DIR, SPI_FLASH_CMD_CNT, SPI_FLASH_DATA_CNT, SPI_FLASH_DMA_ADDR, and SPI_FLASH_TR_DONE.
Referenced by spi_flash_erase().
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Send write disable command to SPI flash.
References M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), SPI_FLASH_BUF1, SPI_FLASH_BUF_DIR, SPI_FLASH_CMD_CNT, SPI_FLASH_DATA_CNT, SPI_FLASH_DMA_ADDR, and SPI_FLASH_TR_DONE.
Referenced by spi_flash_pp().
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Send write enable command to SPI flash.
References M2M_SUCCESS, nm_read_reg_with_ret(), nm_write_reg(), SPI_FLASH_BUF1, SPI_FLASH_BUF_DIR, SPI_FLASH_CMD_CNT, SPI_FLASH_DATA_CNT, SPI_FLASH_DMA_ADDR, and SPI_FLASH_TR_DONE.
Referenced by spi_flash_erase(), and spi_flash_pp().