SAME70 clock configuration.
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_PLL0_DIV 1 |
#define | CONFIG_PLL0_MUL 25 |
#define | CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL |
#define | CONFIG_SYSCLK_DIV 2 |
#define | CONFIG_SYSCLK_PRES SYSCLK_PRES_1 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK |
#define | CONFIG_USBCLK_DIV 1 |
#define | CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL |
#define CONFIG_PLL0_DIV 1 |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_MUL 25 |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL |
Referenced by pll_enable_config_defaults(), sysclk_enable_usb(), and sysclk_init().
#define CONFIG_SYSCLK_DIV 2 |
Referenced by sysclk_get_peripheral_hz(), and sysclk_init().
#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK |
Referenced by sysclk_init().
#define CONFIG_USBCLK_DIV 1 |
Referenced by sysclk_enable_usb().
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL |
Referenced by sysclk_enable_usb().