Chip-specific system clock manager configuration.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_DFLL0_FREQ 48000000UL |
#define | CONFIG_SYSCLK_CPU_DIV 2 |
#define | CONFIG_SYSCLK_PBA_DIV 2 |
#define | CONFIG_SYSCLK_PBB_DIV 2 |
#define | CONFIG_SYSCLK_PBC_DIV 2 |
#define | CONFIG_SYSCLK_PBD_DIV 2 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC80M |
#define CONFIG_DFLL0_FREQ 48000000UL |
Referenced by main().
#define CONFIG_SYSCLK_CPU_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBA_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBB_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBC_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBD_DIV 2 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC80M |
Referenced by sysclk_init().