conf_clock.h File Reference

Chip-specific system clock manager configuration.

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

Macros
#define	CONFIG_CPU_HZ   60000000
#define	CONFIG_GENERIC_CLOCK   3000000
#define	CONFIG_GENERIC_DIV   1
#define	CONFIG_GENERIC_ID   0
#define	CONFIG_GENERIC_SRC   GENCLK_SRC_OSC0
#define	CONFIG_PBA_HZ   30000000
#define	CONFIG_PBB_HZ   30000000
#define	CONFIG_PLL0_DIV   2 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define	CONFIG_PLL0_MUL   10 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define	CONFIG_PLL0_SOURCE   PLL_SRC_OSC0
#define	CONFIG_PLL1_DIV   2 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define	CONFIG_PLL1_MUL   10 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define	CONFIG_PLL1_SOURCE   PLL_SRC_OSC0
#define	CONFIG_SYSCLK_CPU_DIV   0 /* Fcpu = Fsys/(2 ^ CPU_div) */
#define	CONFIG_SYSCLK_PBA_DIV   1 /* Fpba = Fsys/(2 ^ PBA_div) */
#define	CONFIG_SYSCLK_PBB_DIV   1 /* Fpbb = Fsys/(2 ^ PBB_div) */
#define	CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_PLL0
#define	get_generic_clock()
#define	OSC_RCSYS_NOMINAL_HZ   115000
#define	PLL0   0
#define	PLL1   1

#define CONFIG_CPU_HZ   60000000

Referenced by run_sync_clock_test().

#define CONFIG_GENERIC_CLOCK   3000000

Referenced by run_generic_clock_test().

#define CONFIG_GENERIC_DIV   1

Referenced by run_generic_clock_test().

#define CONFIG_GENERIC_ID   0

Referenced by cleanup_generic_clock_test(), and run_generic_clock_test().

#define CONFIG_GENERIC_SRC   GENCLK_SRC_OSC0

Referenced by run_generic_clock_test().

#define CONFIG_PBA_HZ   30000000

Referenced by run_sync_clock_test().

#define CONFIG_PBB_HZ   30000000

Referenced by run_sync_clock_test().

#define CONFIG_PLL0_DIV   2 /* Fpll = (Fclk * PLL_mul) / PLL_div */

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_MUL   10 /* Fpll = (Fclk * PLL_mul) / PLL_div */

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_SOURCE   PLL_SRC_OSC0

Referenced by pll_enable_config_defaults(), and run_pll_dfll_test().

#define CONFIG_PLL1_DIV   2 /* Fpll = (Fclk * PLL_mul) / PLL_div */

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL1_MUL   10 /* Fpll = (Fclk * PLL_mul) / PLL_div */

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL1_SOURCE   PLL_SRC_OSC0

Referenced by pll_enable_config_defaults(), and run_pll_dfll_test().

#define CONFIG_SYSCLK_CPU_DIV   0 /* Fcpu = Fsys/(2 ^ CPU_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBA_DIV   1 /* Fpba = Fsys/(2 ^ PBA_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBB_DIV   1 /* Fpbb = Fsys/(2 ^ PBB_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_PLL0

Referenced by sysclk_init().

#define get_generic_clock

(

)

Value:

(CONFIG_GENERIC_DIV == 0 ? osc_get_rate(OSC_ID_OSC0) \
    : osc_get_rate(OSC_ID_OSC0) / (2*(CONFIG_GENERIC_DIV + 1)))

Referenced by run_generic_clock_test().

#define OSC_RCSYS_NOMINAL_HZ   115000

Referenced by run_osc32_test().

#define PLL0   0

Referenced by cleanup_pll_dfll_test(), and run_pll_dfll_test().

#define PLL1   1

Referenced by cleanup_pll_dfll_test(), and run_pll_dfll_test().