conf_clock.h File Reference

Chip-specific system clock manager configuration.

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

Macros
#define	CONFIG_CPU_HZ   48012500
#define	CONFIG_DFLL0_DIV   1 /* Fdfll = (Fclk * mul) / div */
#define	CONFIG_DFLL0_MUL   835 /* Fdfll = (Fclk * mul) / div */
#define	CONFIG_DFLL0_SOURCE   GENCLK_SRC_RCSYS
#define	CONFIG_GENERIC_CLOCK   28750
#define	CONFIG_GENERIC_DIV   1
#define	CONFIG_GENERIC_ID   2
#define	CONFIG_GENERIC_SRC   GENCLK_SRC_RCSYS
#define	CONFIG_PBA_HZ   24006250
#define	CONFIG_PBB_HZ   24006250
#define	CONFIG_SYSCLK_CPU_DIV   1 /* Fcpu = Fsys/(2 ^ CPU_div) */
#define	CONFIG_SYSCLK_PBA_DIV   2 /* Fpba = Fsys/(2 ^ PBA_div) */
#define	CONFIG_SYSCLK_PBB_DIV   2 /* Fpbb = Fsys/(2 ^ PBB_div) */
#define	CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_DFLL
#define	get_generic_clock()
#define	OSC_RCSYS_NOMINAL_HZ   115000
#define	PLL0   0
#define	PLL1   1

#define CONFIG_CPU_HZ   48012500

Referenced by run_sync_clock_test().

#define CONFIG_DFLL0_DIV   1 /* Fdfll = (Fclk * mul) / div */

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_MUL   835 /* Fdfll = (Fclk * mul) / div */

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_SOURCE   GENCLK_SRC_RCSYS

Referenced by dfll_enable_config_defaults().

#define CONFIG_GENERIC_CLOCK   28750

Referenced by run_generic_clock_test().

#define CONFIG_GENERIC_DIV   1

Referenced by run_generic_clock_test().

#define CONFIG_GENERIC_ID   2

Referenced by cleanup_generic_clock_test(), and run_generic_clock_test().

#define CONFIG_GENERIC_SRC   GENCLK_SRC_RCSYS

Referenced by run_generic_clock_test().

#define CONFIG_PBA_HZ   24006250

Referenced by run_sync_clock_test().

#define CONFIG_PBB_HZ   24006250

Referenced by run_sync_clock_test().

#define CONFIG_SYSCLK_CPU_DIV   1 /* Fcpu = Fsys/(2 ^ CPU_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBA_DIV   2 /* Fpba = Fsys/(2 ^ PBA_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBB_DIV   2 /* Fpbb = Fsys/(2 ^ PBB_div) */

Referenced by sysclk_init().

#define CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_DFLL

Referenced by sysclk_init().

#define get_generic_clock

(

)

Value:

(CONFIG_GENERIC_DIV == 0 ? osc_get_rate(OSC_ID_RCSYS) \
    : osc_get_rate(OSC_ID_RCSYS) / (2*(CONFIG_GENERIC_DIV + 1)))

Referenced by run_generic_clock_test().

#define OSC_RCSYS_NOMINAL_HZ   115000

Referenced by dfll_priv_get_source_hz(), run_osc32_test(), and sysclk_get_main_hz().

#define PLL0   0

Referenced by cleanup_pll_dfll_test(), and run_pll_dfll_test().

#define PLL1   1

Referenced by cleanup_pll_dfll_test(), and run_pll_dfll_test().