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SAM System Clock Management (SYSTEM CLOCK) Driver

This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's clocking related functions.

This includes the various clock sources, bus clocks, and generic clocks within the device, with functions to manage the enabling, disabling, source selection, and prescaling of clocks to various internal peripherals.

The following peripherals are used by this module:

The following devices can use this module:

The outline of this documentation is as follows:

Prerequisites

There are no prerequisites for this module.

Module Overview

The SAM devices contain a sophisticated clocking system, which is designed to give the maximum flexibility to the user application. This system allows a system designer to tune the performance and power consumption of the device in a dynamic manner, to achieve the best trade-off between the two for a particular application.

This driver provides a set of functions for the configuration and management of the various clock related functionalities within the device.

Clock Sources

The SAM devices have a number of master clock source modules, each of which being capable of producing a stabilized output frequency which can then be fed into the various peripherals and modules within the device.

Possible clock source modules include internal R/C oscillators, internal DFLL modules, as well as external crystal oscillators and/or clock inputs.

CPU / Bus Clocks

The CPU and AHB/APBx buses are clocked by the same physical clock source (referred in this module as the Main Clock). The CPU and bus clocks are divided into a number of clock domains. Each clock domain can run at different frequencies.

There are three clock domains:

Each clock domain (CPU, LP, BUP) can be changed on the fly. To ensure correct operation, frequencies must be selected so that BUPDIV ≥ LPDIV ≥ HSDIV. Also, frequencies must never exceed the specified maximum frequency for each clock domain. A module may be connected to several clock domains (for instance, AHB and APB).

The general main clock tree for the CPU and associated buses is shown in the figure below.

Clock Masking

To save power, the input clock to one or more peripherals on the AHB and APBx buses can be masked away. When masked, no clock is passed into the module. Disabling of clocks of unused modules will prevent all access to the masked module, but will reduce the overall device power consumption.

Generic Clocks

Within the SAM devices are a number of Generic Clocks; these are used to provide clocks to the various peripheral clock domains in the device in a standardized manner. One or more master source clocks can be selected as the input clock to a Generic Clock Generator, which can prescale down the input frequency to a slower rate for use in a peripheral.

Additionally, a number of individually selectable Generic Clock Channels are provided, which multiplex and gate the various generator outputs for one or more peripherals within the device. This setup allows for a single common generator to feed one or more channels, which can then be enabled or disabled individually as required.

Clock Chain Example

An example setup of a complete clock chain within the device is shown in the figure below.

Generic Clock Generators

Each Generic Clock generator within the device can source its input clock from one of the provided Source Clocks, and prescale the output for one or more Generic Clock Channels in a one-to-many relationship. The generators thus allow for several clocks to be generated of different frequencies, power usages, and accuracies, which can be turned on and off individually to disable the clocks to multiple peripherals as a group.

Generic Clock Channels

To connect a Generic Clock Generator to a peripheral within the device, a Generic Clock Channel is used. Each peripheral or peripheral group has an associated Generic Clock Channel, which serves as the clock input for the peripheral(s). To supply a clock to the peripheral module(s), the associated channel must be connected to a running Generic Clock Generator and the channel enabled.

Special Considerations

There are no special considerations for this module.

Extra Information

For extra information, see Extra Information for SYSTEM CLOCK Driver. This includes:

Examples

For a list of examples related to this driver, see Examples for System Clock Driver.

API Overview

Data Structures

struct  system_clock_source_dfll_config
 Configuration structure for DFLL. More...
 
struct  system_clock_source_dpll_config
 Configuration structure for DPLL. More...
 
struct  system_clock_source_osc16m_config
 Configuration structure for OSC16M. More...
 
struct  system_clock_source_osc32k_config
 Configuration structure for OSCULP32K. More...
 
struct  system_clock_source_osculp32k_config
 Configuration structure for OSCULP32K. More...
 
struct  system_clock_source_xosc32k_config
 Configuration structure for XOSC32K. More...
 
struct  system_clock_source_xosc_config
 Configuration structure for XOSC. More...
 
struct  system_gclk_chan_config
 Generic Clock configuration structure. More...
 
struct  system_gclk_gen_config
 Generic Clock Generator configuration structure. More...
 

Enumerations

enum  gclk_generator {
  GCLK_GENERATOR_0,
  GCLK_GENERATOR_1,
  GCLK_GENERATOR_2,
  GCLK_GENERATOR_3,
  GCLK_GENERATOR_4,
  GCLK_GENERATOR_5,
  GCLK_GENERATOR_6,
  GCLK_GENERATOR_7,
  GCLK_GENERATOR_8,
  GCLK_GENERATOR_9,
  GCLK_GENERATOR_10,
  GCLK_GENERATOR_11,
  GCLK_GENERATOR_12,
  GCLK_GENERATOR_13,
  GCLK_GENERATOR_14,
  GCLK_GENERATOR_15,
  GCLK_GENERATOR_16
}
 List of available GCLK generators. More...
 
enum  system_clock_apb_bus {
  SYSTEM_CLOCK_APB_APBA,
  SYSTEM_CLOCK_APB_APBB,
  SYSTEM_CLOCK_APB_APBC,
  SYSTEM_CLOCK_APB_APBD,
  SYSTEM_CLOCK_APB_APBE
}
 List of APB peripheral buses. More...
 
enum  system_clock_dfll_chill_cycle {
  SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
  SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = OSCCTRL_DFLLCTRL_CCDIS
}
 Chill cycle behavior of the DFLL module. More...
 
enum  system_clock_dfll_loop_mode {
  SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
  SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = OSCCTRL_DFLLCTRL_MODE
}
 Operating modes of the DFLL clock source. More...
 
enum  system_clock_dfll_quick_lock {
  SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
  SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = OSCCTRL_DFLLCTRL_QLDIS
}
 QuickLock settings for the DFLL module. More...
 
enum  system_clock_dfll_stable_tracking {
  SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
  SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = OSCCTRL_DFLLCTRL_STABLE
}
 Fine tracking behavior for the DFLL once a lock has been acquired. More...
 
enum  system_clock_dfll_wakeup_lock {
  SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
  SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = OSCCTRL_DFLLCTRL_LLAW
}
 Locking behavior for the DFLL during device wake-up. More...
 
enum  system_clock_external {
  SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
  SYSTEM_CLOCK_EXTERNAL_CLOCK
}
 External clock source types. More...
 
enum  system_clock_source {
  SYSTEM_CLOCK_SOURCE_OSC16M = GCLK_SOURCE_OSC16M,
  SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
  SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC,
  SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
  SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
  SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
  SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
  SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
  SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL
}
 Available clock sources in the system. More...
 
enum  system_clock_source_dpll_filter {
  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER
}
 Filter type of the DPLL module. More...
 
enum  system_clock_source_dpll_lock_time {
  SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
  SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
  SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
  SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
  SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS
}
 Lock time-out value of the DPLL module. More...
 
enum  system_clock_source_dpll_prescaler {
  SYSTEM_CLOCK_SOURCE_DPLL_DIV_1,
  SYSTEM_CLOCK_SOURCE_DPLL_DIV_2,
  SYSTEM_CLOCK_SOURCE_DPLL_DIV_4
}
 DPLL Output Clock Prescaler. More...
 
enum  system_clock_source_dpll_reference_clock {
  SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
  SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
  SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK
}
 Reference clock source of the DPLL module. More...
 
enum  system_main_clock_div {
  SYSTEM_MAIN_CLOCK_DIV_1,
  SYSTEM_MAIN_CLOCK_DIV_2,
  SYSTEM_MAIN_CLOCK_DIV_4,
  SYSTEM_MAIN_CLOCK_DIV_8,
  SYSTEM_MAIN_CLOCK_DIV_16,
  SYSTEM_MAIN_CLOCK_DIV_32,
  SYSTEM_MAIN_CLOCK_DIV_64,
  SYSTEM_MAIN_CLOCK_DIV_128
}
 Main CPU, Lowpower and Backup clock division. More...
 
enum  system_osc16m_fsel {
  SYSTEM_OSC16M_4M,
  SYSTEM_OSC16M_8M,
  SYSTEM_OSC16M_12M,
  SYSTEM_OSC16M_16M
}
 Frequency selection for the internal 16MHz system clock. More...
 
enum  system_osc32k_startup {
  SYSTEM_OSC32K_STARTUP_3,
  SYSTEM_OSC32K_STARTUP_4,
  SYSTEM_OSC32K_STARTUP_6,
  SYSTEM_OSC32K_STARTUP_10,
  SYSTEM_OSC32K_STARTUP_18,
  SYSTEM_OSC32K_STARTUP_34,
  SYSTEM_OSC32K_STARTUP_66,
  SYSTEM_OSC32K_STARTUP_130
}
 Available start-up times for the OSC32K. More...
 
enum  system_xosc32k_startup {
  SYSTEM_XOSC32K_STARTUP_2048,
  SYSTEM_XOSC32K_STARTUP_4096,
  SYSTEM_XOSC32K_STARTUP_16384,
  SYSTEM_XOSC32K_STARTUP_32768,
  SYSTEM_XOSC32K_STARTUP_65536,
  SYSTEM_XOSC32K_STARTUP_131072,
  SYSTEM_XOSC32K_STARTUP_262144
}
 Available start-up times for the XOSC32K. More...
 
enum  system_xosc_startup {
  SYSTEM_XOSC_STARTUP_1,
  SYSTEM_XOSC_STARTUP_2,
  SYSTEM_XOSC_STARTUP_4,
  SYSTEM_XOSC_STARTUP_8,
  SYSTEM_XOSC_STARTUP_16,
  SYSTEM_XOSC_STARTUP_32,
  SYSTEM_XOSC_STARTUP_64,
  SYSTEM_XOSC_STARTUP_128,
  SYSTEM_XOSC_STARTUP_256,
  SYSTEM_XOSC_STARTUP_512,
  SYSTEM_XOSC_STARTUP_1024,
  SYSTEM_XOSC_STARTUP_2048,
  SYSTEM_XOSC_STARTUP_4096,
  SYSTEM_XOSC_STARTUP_8192,
  SYSTEM_XOSC_STARTUP_16384,
  SYSTEM_XOSC_STARTUP_32768
}
 Available start-up times for the XOSC. More...
 

External Oscillator Management

static void system_clock_source_xosc_get_config_defaults (struct system_clock_source_xosc_config *const config)
 Retrieve the default configuration for XOSC. More...
 
void system_clock_source_xosc_set_config (struct system_clock_source_xosc_config *const config)
 Configure the external oscillator clock source. More...
 

External 32KHz Oscillator Management

static void system_clock_source_xosc32k_get_config_defaults (struct system_clock_source_xosc32k_config *const config)
 Retrieve the default configuration for XOSC32K. More...
 
void system_clock_source_xosc32k_set_config (struct system_clock_source_xosc32k_config *const config)
 Configure the XOSC32K external 32KHz oscillator clock source. More...
 

Internal 32KHz Oscillator Management

static void system_clock_source_osc32k_get_config_defaults (struct system_clock_source_osc32k_config *const config)
 Retrieve the default configuration for OSC32K. More...
 
void system_clock_source_osc32k_set_config (struct system_clock_source_osc32k_config *const config)
 Configure the internal OSC32K oscillator clock source. More...
 

Internal Ultra Low Power 32KHz Oscillator Management

static void system_clock_source_osculp32k_get_config_defaults (struct system_clock_source_osculp32k_config *const config)
 Retrieve the default configuration for OSCULP32K. More...
 
void system_clock_source_osculp32k_set_config (struct system_clock_source_osculp32k_config *const config)
 Configure the internal OSCULP32K oscillator clock source. More...
 

Internal 16MHz Oscillator Management

static void system_clock_source_osc16m_get_config_defaults (struct system_clock_source_osc16m_config *const config)
 Retrieve the default configuration for OSC16M. More...
 
void system_clock_source_osc16m_set_config (struct system_clock_source_osc16m_config *const config)
 Configure the internal OSC16M oscillator clock source. More...
 

Internal DFLL Management

static void system_clock_source_dfll_get_config_defaults (struct system_clock_source_dfll_config *const config)
 Retrieve the default configuration for DFLL. More...
 
void system_clock_source_dfll_set_config (struct system_clock_source_dfll_config *const config)
 Configure the DFLL clock source. More...
 

Clock Source Management

enum status_code system_clock_source_write_calibration (const enum system_clock_source system_clock_source, const uint16_t calibration_value, const uint8_t freq_range)
 
enum status_code system_clock_source_enable (const enum system_clock_source system_clock_source)
 
enum status_code system_clock_source_disable (const enum system_clock_source clk_source)
 Disables a clock source. More...
 
bool system_clock_source_is_ready (const enum system_clock_source clk_source)
 Checks if a clock source is ready. More...
 
uint32_t system_clock_source_get_hz (const enum system_clock_source clk_source)
 Retrieve the frequency of a clock source. More...
 

Main Clock Management

static void system_main_clock_set_failure_detect (const bool enable)
 Enable or disable the main clock failure detection. More...
 
static void system_cpu_clock_set_divider (const enum system_main_clock_div divider)
 Set main CPU clock divider. More...
 
static void system_low_power_clock_set_divider (const enum system_main_clock_div divider)
 Set Low-Power Clock divider. More...
 
static void system_backup_clock_set_divider (const enum system_main_clock_div divider)
 Set Backup Clock divider. More...
 
static uint32_t system_cpu_clock_get_hz (void)
 Retrieves the current frequency of the CPU core. More...
 
static uint32_t system_low_power_clock_get_hz (void)
 Retrieves the current frequency of Low-Power clock. More...
 
static uint32_t system_backup_clock_get_hz (void)
 Retrieves the current frequency of backup clock. More...
 

Bus Clock Masking

static void system_ahb_clock_set_mask (const uint32_t ahb_mask)
 Set bits in the clock mask for the AHB bus. More...
 
static void system_ahb_clock_clear_mask (const uint32_t ahb_mask)
 Clear bits in the clock mask for the AHB bus. More...
 
static enum status_code system_apb_clock_set_mask (const enum system_clock_apb_bus bus, const uint32_t mask)
 Set bits in the clock mask for an APBx bus. More...
 
static enum status_code system_apb_clock_clear_mask (const enum system_clock_apb_bus bus, const uint32_t mask)
 Clear bits in the clock mask for an APBx bus. More...
 

Internal DPLL Management

static void system_clock_source_dpll_get_config_defaults (struct system_clock_source_dpll_config *const config)
 Retrieve the default configuration for DPLL. More...
 
void system_clock_source_dpll_set_config (struct system_clock_source_dpll_config *const config)
 Configure the DPLL clock source. More...
 

System Clock Initialization

void system_clock_init (void)
 Initialize clock system based on the configuration in conf_clocks.h. More...
 

System Flash Wait States

static void system_flash_set_waitstates (uint8_t wait_states)
 Set flash controller wait states. More...
 

Generic Clock Management

void system_gclk_init (void)
 Initializes the GCLK driver. More...
 

Generic Clock Management (Generators)

static void system_gclk_gen_get_config_defaults (struct system_gclk_gen_config *const config)
 Initializes a Generic Clock Generator configuration structure to defaults. More...
 
void system_gclk_gen_set_config (const uint8_t generator, struct system_gclk_gen_config *const config)
 Writes a Generic Clock Generator configuration to the hardware module. More...
 
void system_gclk_gen_enable (const uint8_t generator)
 Enables a Generic Clock Generator that was previously configured. More...
 
void system_gclk_gen_disable (const uint8_t generator)
 Disables a Generic Clock Generator that was previously enabled. More...
 
bool system_gclk_gen_is_enabled (const uint8_t generator)
 Determins if the specified Generic Clock Generator is enabled. More...
 

Generic Clock Management (Channels)

static void system_gclk_chan_get_config_defaults (struct system_gclk_chan_config *const config)
 Initializes a Generic Clock configuration structure to defaults. More...
 
void system_gclk_chan_set_config (const uint8_t channel, struct system_gclk_chan_config *const config)
 Writes a Generic Clock configuration to the hardware module. More...
 
void system_gclk_chan_enable (const uint8_t channel)
 Enables a Generic Clock that was previously configured. More...
 
void system_gclk_chan_disable (const uint8_t channel)
 Disables a Generic Clock that was previously enabled. More...
 
bool system_gclk_chan_is_enabled (const uint8_t channel)
 Determins if the specified Generic Clock channel is enabled. More...
 
void system_gclk_chan_lock (const uint8_t channel)
 Locks a Generic Clock channel from further configuration writes. More...
 
bool system_gclk_chan_is_locked (const uint8_t channel)
 Determins if the specified Generic Clock channel is locked. More...
 

Generic Clock Frequency Retrieval

uint32_t system_gclk_gen_get_hz (const uint8_t generator)
 Retrieves the clock frequency of a Generic Clock generator. More...
 
uint32_t system_gclk_chan_get_hz (const uint8_t channel)
 Retrieves the clock frequency of a Generic Clock channel. More...
 

List of available GCLK generators.

List of Available GCLK generators. This enum is used in the peripheral device drivers to select the GCLK generator to be used for its operation.

The number of GCLK generators available is device dependent.

Enumerator
GCLK_GENERATOR_0 

GCLK generator channel 0.

GCLK_GENERATOR_1 

GCLK generator channel 1.

GCLK_GENERATOR_2 

GCLK generator channel 2.

GCLK_GENERATOR_3 

GCLK generator channel 3.

GCLK_GENERATOR_4 

GCLK generator channel 4.

GCLK_GENERATOR_5 

GCLK generator channel 5.

GCLK_GENERATOR_6 

GCLK generator channel 6.

GCLK_GENERATOR_7 

GCLK generator channel 7.

GCLK_GENERATOR_8 

GCLK generator channel 8.

GCLK_GENERATOR_9 

GCLK generator channel 9.

GCLK_GENERATOR_10 

GCLK generator channel 10.

GCLK_GENERATOR_11 

GCLK generator channel 11.

GCLK_GENERATOR_12 

GCLK generator channel 12.

GCLK_GENERATOR_13 

GCLK generator channel 13.

GCLK_GENERATOR_14 

GCLK generator channel 14.

GCLK_GENERATOR_15 

GCLK generator channel 15.

GCLK_GENERATOR_16 

GCLK generator channel 16.

List of APB peripheral buses.

Available bus clock domains on the APB bus.

Enumerator
SYSTEM_CLOCK_APB_APBA 

Peripheral bus A on the APB bus.

SYSTEM_CLOCK_APB_APBB 

Peripheral bus B on the APB bus.

SYSTEM_CLOCK_APB_APBC 

Peripheral bus C on the APB bus.

SYSTEM_CLOCK_APB_APBD 

Peripheral bus D on the APB bus.

SYSTEM_CLOCK_APB_APBE 

Peripheral bus E on the APB bus.

Chill cycle behavior of the DFLL module.

DFLL chill cycle behavior modes of the DFLL module. A chill cycle is a period of time when the DFLL output frequency is not measured by the unit, to allow the output to stabilize after a change in the input clock source.

Enumerator
SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE 

Enable a chill cycle, where the DFLL output frequency is not measured.

SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE 

Disable a chill cycle, where the DFLL output frequency is not measured.

Operating modes of the DFLL clock source.

Available operating modes of the DFLL clock source module.

Enumerator
SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN 

The DFLL is operating in open loop mode with no feedback.

SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED 

The DFLL is operating in closed loop mode with frequency feedback from a low frequency reference clock.

QuickLock settings for the DFLL module.

DFLL QuickLock settings for the DFLL module, to allow for a faster lock of the DFLL output frequency at the expense of accuracy.

Enumerator
SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE 

Enable the QuickLock feature for looser lock requirements on the DFLL.

SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE 

Disable the QuickLock feature for strict lock requirements on the DFLL.

Fine tracking behavior for the DFLL once a lock has been acquired.

DFLL fine tracking behavior modes after a lock has been acquired.

Enumerator
SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK 

Keep tracking after the DFLL has gotten a fine lock.

SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK 

Stop tracking after the DFLL has gotten a fine lock.

Locking behavior for the DFLL during device wake-up.

DFLL lock behavior modes on device wake-up from sleep.

Enumerator
SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP 

Keep DFLL lock when the device wakes from sleep.

SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE 

Lose DFLL lock when the devices wakes from sleep.

External clock source types.

Available external clock source types.

Enumerator
SYSTEM_CLOCK_EXTERNAL_CRYSTAL 

The external clock source is a crystal oscillator.

SYSTEM_CLOCK_EXTERNAL_CLOCK 

The connected clock source is an external logic level clock signal.

Available clock sources in the system.

Clock sources available to the GCLK generators.

Enumerator
SYSTEM_CLOCK_SOURCE_OSC16M 

Internal 16MHz RC oscillator.

SYSTEM_CLOCK_SOURCE_OSC32K 

Internal 32KHz RC oscillator.

SYSTEM_CLOCK_SOURCE_XOSC 

External oscillator.

SYSTEM_CLOCK_SOURCE_XOSC32K 

External 32KHz oscillator.

SYSTEM_CLOCK_SOURCE_DFLL 

Digital Frequency Locked Loop (DFLL)

SYSTEM_CLOCK_SOURCE_ULP32K 

Internal Ultra Low Power 32KHz oscillator.

SYSTEM_CLOCK_SOURCE_GCLKIN 

Generator input pad.

SYSTEM_CLOCK_SOURCE_GCLKGEN1 

Generic clock generator one output.

SYSTEM_CLOCK_SOURCE_DPLL 

Digital Phase Locked Loop (DPLL)

Filter type of the DPLL module.

Enumerator
SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT 

Default filter mode.

SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER 

Low bandwidth filter.

SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER 

High bandwidth filter.

SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER 

High damping filter.

Lock time-out value of the DPLL module.

Enumerator
SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT 

Set no time-out as default.

SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS 

Set time-out if no lock within 8ms.

SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS 

Set time-out if no lock within 9ms.

SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS 

Set time-out if no lock within 10ms.

SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS 

Set time-out if no lock within 11ms.

DPLL Output Clock Prescaler.

Enumerator
SYSTEM_CLOCK_SOURCE_DPLL_DIV_1 

DPLL output is divided by 1.

SYSTEM_CLOCK_SOURCE_DPLL_DIV_2 

DPLL output is divided by 2.

SYSTEM_CLOCK_SOURCE_DPLL_DIV_4 

DPLL output is divided by 4.

Reference clock source of the DPLL module.

Enumerator
SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K 

Select XOSC32K as clock reference.

SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC 

Select XOSC as clock reference.

SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK 

Select GCLK as clock reference.

Main CPU, Lowpower and Backup clock division.

Available division ratios for the CPU and Lowpower and Backup clocks.

Enumerator
SYSTEM_MAIN_CLOCK_DIV_1 

Divide Main clock by one.

SYSTEM_MAIN_CLOCK_DIV_2 

Divide Main clock by two.

SYSTEM_MAIN_CLOCK_DIV_4 

Divide Main clock by four.

SYSTEM_MAIN_CLOCK_DIV_8 

Divide Main clock by eight.

SYSTEM_MAIN_CLOCK_DIV_16 

Divide Main clock by 16.

SYSTEM_MAIN_CLOCK_DIV_32 

Divide Main clock by 32.

SYSTEM_MAIN_CLOCK_DIV_64 

Divide Main clock by 64.

SYSTEM_MAIN_CLOCK_DIV_128 

Divide Main clock by 128.

Frequency selection for the internal 16MHz system clock.

Available frequency selection for the internal 16MHz (nominal) system clock.

Enumerator
SYSTEM_OSC16M_4M 

Frequency Selection 4MHz.

SYSTEM_OSC16M_8M 

Frequency Selection 8MHz.

SYSTEM_OSC16M_12M 

Frequency Selection 12MHz.

SYSTEM_OSC16M_16M 

Frequency Selection 16MHz.

Available start-up times for the OSC32K.

Available internal 32KHz oscillator start-up times, as a number of internal OSC32K clock cycles.

Enumerator
SYSTEM_OSC32K_STARTUP_3 

Wait three clock cycles until the clock source is considered stable.

SYSTEM_OSC32K_STARTUP_4 

Wait four clock cycles until the clock source is considered stable.

SYSTEM_OSC32K_STARTUP_6 

Wait six clock cycles until the clock source is considered stable.

SYSTEM_OSC32K_STARTUP_10 

Wait ten clock cycles until the clock source is considered stable.

SYSTEM_OSC32K_STARTUP_18 

Wait 18 clock cycles until the clock source is considered stable.

SYSTEM_OSC32K_STARTUP_34 

Wait 34 clock cycles until the clock source is considered stable.

SYSTEM_OSC32K_STARTUP_66 

Wait 66 clock cycles until the clock source is considered stable.

SYSTEM_OSC32K_STARTUP_130 

Wait 130 clock cycles until the clock source is considered stable.

Available start-up times for the XOSC32K.

Available external 32KHz oscillator start-up times, as a number of external clock cycles.

Enumerator
SYSTEM_XOSC32K_STARTUP_2048 

Wait 2048 clock cycles until the clock source is considered stable.

SYSTEM_XOSC32K_STARTUP_4096 

Wait 4096 clock cycles until the clock source is considered stable.

SYSTEM_XOSC32K_STARTUP_16384 

Wait 16384 clock cycles until the clock source is considered stable.

SYSTEM_XOSC32K_STARTUP_32768 

Wait 32768 clock cycles until the clock source is considered stable.

SYSTEM_XOSC32K_STARTUP_65536 

Wait 65536 clock cycles until the clock source is considered stable.

SYSTEM_XOSC32K_STARTUP_131072 

Wait 131072 clock cycles until the clock source is considered stable.

SYSTEM_XOSC32K_STARTUP_262144 

Wait 262144 clock cycles until the clock source is considered stable.

Available start-up times for the XOSC.

Available external oscillator start-up times, as a number of external clock cycles.

Enumerator
SYSTEM_XOSC_STARTUP_1 

Wait one clock cycle until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_2 

Wait two clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_4 

Wait four clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_8 

Wait eight clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_16 

Wait 16 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_32 

Wait 32 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_64 

Wait 64 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_128 

Wait 128 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_256 

Wait 256 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_512 

Wait 512 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_1024 

Wait 1024 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_2048 

Wait 2048 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_4096 

Wait 4096 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_8192 

Wait 8192 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_16384 

Wait 16384 clock cycles until the clock source is considered stable.

SYSTEM_XOSC_STARTUP_32768 

Wait 32768 clock cycles until the clock source is considered stable.

static void system_ahb_clock_clear_mask ( const uint32_t  ahb_mask)
inlinestatic

Clear bits in the clock mask for the AHB bus.

This function will clear bits in the clock mask for the AHB bus. Any bits set to 1 will disable that clock, zero bits in the mask will be ignored.

Parameters
[in]ahb_maskAHB clock mask
static void system_ahb_clock_set_mask ( const uint32_t  ahb_mask)
inlinestatic

Set bits in the clock mask for the AHB bus.

This function will set bits in the clock mask for the AHB bus. Any bits set to 1 will enable that clock, 0 bits in the mask will be ignored

Parameters
[in]ahb_maskAHB clock mask
static enum status_code system_apb_clock_clear_mask ( const enum system_clock_apb_bus  bus,
const uint32_t  mask 
)
inlinestatic

Clear bits in the clock mask for an APBx bus.

This function will clear bits in the clock mask for an APBx bus. Any bits set to 1 will disable the corresponding module clock, zero bits in the mask will be ignored.

Parameters
[in]maskAPBx clock mask, a SYSTEM_CLOCK_APB_APBx constant from the device header files
[in]busBus to clear clock mask bits
Returns
Status indicating the result of the clock mask change operation.
Return values
STATUS_ERR_INVALID_ARGInvalid bus ID was given
STATUS_OKThe clock mask was changed successfully

References Assert, STATUS_ERR_INVALID_ARG, STATUS_OK, SYSTEM_CLOCK_APB_APBA, SYSTEM_CLOCK_APB_APBB, SYSTEM_CLOCK_APB_APBC, SYSTEM_CLOCK_APB_APBD, and SYSTEM_CLOCK_APB_APBE.

static enum status_code system_apb_clock_set_mask ( const enum system_clock_apb_bus  bus,
const uint32_t  mask 
)
inlinestatic

Set bits in the clock mask for an APBx bus.

This function will set bits in the clock mask for an APBx bus. Any bits set to 1 will enable the corresponding module clock, zero bits in the mask will be ignored.

Parameters
[in]maskAPBx clock mask, a SYSTEM_CLOCK_APB_APBx constant from the device header files
[in]busBus to set clock mask bits for, a mask of PM_APBxMASK_* constants from the device header files
Returns
Status indicating the result of the clock mask change operation.
Return values
STATUS_ERR_INVALID_ARGInvalid bus given
STATUS_OKThe clock mask was set successfully

References Assert, STATUS_ERR_INVALID_ARG, STATUS_OK, SYSTEM_CLOCK_APB_APBA, SYSTEM_CLOCK_APB_APBB, SYSTEM_CLOCK_APB_APBC, SYSTEM_CLOCK_APB_APBD, and SYSTEM_CLOCK_APB_APBE.

Referenced by _system_extint_init(), system_gclk_init(), and usb_init().

static uint32_t system_backup_clock_get_hz ( void  )
inlinestatic

Retrieves the current frequency of backup clock.

Retrieves the operating frequency of backup clock, obtained from backup clock and the set backup clock divider.

Returns
Current CPU frequency in Hz.

References GCLK_GENERATOR_0, and system_gclk_gen_get_hz().

static void system_backup_clock_set_divider ( const enum system_main_clock_div  divider)
inlinestatic

Set Backup Clock divider.

Sets the clock divider used on the main clock to provide the CPU clock.

Parameters
[in]dividerCPU clock divider

Referenced by system_clock_init().

void system_clock_init ( void  )

Initialize clock system based on the configuration in conf_clocks.h.

This function will apply the settings in conf_clocks.h when run from the user application. All clock sources and GCLK generators are running when this function returns.

Note
OSC16M is always enabled and if user selects other clocks for GCLK generators, the OSC16M default enable can be disabled after system_clock_init. Make sure the clock switches successfully before disabling OSC8M.

References _system_clock_source_osc16m_freq_sel(), Assert, system_clock_source_dfll_config::chill_cycle, system_clock_source_dfll_config::coarse_max_step, system_clock_source_dfll_config::coarse_value, CONF_CLOCK_BACKUP_DIVIDER, CONF_CLOCK_CONFIGURE_GCLK, CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT, CONF_CLOCK_CPU_DIVIDER, CONF_CLOCK_DFLL_FINE_VALUE, CONF_CLOCK_DFLL_LOOP_MODE, CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE, CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE, CONF_CLOCK_DFLL_MULTIPLY_FACTOR, CONF_CLOCK_DFLL_ON_DEMAND, CONF_CLOCK_DFLL_RUN_IN_STANDBY, CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR, CONF_CLOCK_DPLL_FILTER, CONF_CLOCK_DPLL_LOCK_BYPASS, CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR, CONF_CLOCK_DPLL_LOCK_TIME, CONF_CLOCK_DPLL_LOW_POWER_ENABLE, CONF_CLOCK_DPLL_ON_DEMAND, CONF_CLOCK_DPLL_OUTPUT_FREQUENCY, CONF_CLOCK_DPLL_PRESCALER, CONF_CLOCK_DPLL_REFERENCE_CLOCK, CONF_CLOCK_DPLL_REFERENCE_DIVIDER, CONF_CLOCK_DPLL_REFERENCE_FREQUENCY, CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR, CONF_CLOCK_DPLL_RUN_IN_STANDBY, CONF_CLOCK_DPLL_WAKE_UP_FAST, CONF_CLOCK_FLASH_WAIT_STATES, CONF_CLOCK_LOW_POWER_DIVIDER, CONF_CLOCK_OSC16M_FREQ_SEL, CONF_CLOCK_OSC16M_ON_DEMAND, CONF_CLOCK_OSC16M_RUN_IN_STANDBY, CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT, CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT, CONF_CLOCK_OSC32K_ON_DEMAND, CONF_CLOCK_OSC32K_RUN_IN_STANDBY, CONF_CLOCK_OSC32K_STARTUP_TIME, CONF_CLOCK_XOSC32K_ENABLE, CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT, CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT, CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL, CONF_CLOCK_XOSC32K_ON_DEMAND, CONF_CLOCK_XOSC32K_RUN_IN_STANDBY, CONF_CLOCK_XOSC32K_STARTUP_TIME, CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL, CONF_CLOCK_XOSC_ENABLE, CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL, CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY, CONF_CLOCK_XOSC_ON_DEMAND, CONF_CLOCK_XOSC_RUN_IN_STANDBY, CONF_CLOCK_XOSC_STARTUP_TIME, system_clock_source_xosc32k_config::enable_1khz_output, system_clock_source_osc32k_config::enable_1khz_output, system_clock_source_xosc32k_config::enable_32khz_output, system_clock_source_osc32k_config::enable_32khz_output, system_clock_source_xosc32k_config::external_clock, system_clock_source_xosc_config::external_clock, system_clock_source_dpll_config::filter, system_clock_source_dfll_config::fine_max_step, system_clock_source_dfll_config::fine_value, system_clock_source_xosc_config::frequency, system_clock_source_xosc32k_config::frequency, system_clock_source_dpll_config::lock_bypass, system_clock_source_dpll_config::lock_time, system_clock_source_dfll_config::loop_mode, system_clock_source_dpll_config::low_power_enable, MREPEAT, system_clock_source_dfll_config::multiply_factor, NVM_DFLL_COARSE_POS, NVM_DFLL_COARSE_SIZE, system_clock_source_xosc32k_config::on_demand, system_clock_source_osc32k_config::on_demand, system_clock_source_dfll_config::on_demand, system_clock_source_dpll_config::on_demand, system_clock_source_dpll_config::output_frequency, system_clock_source_dpll_config::prescaler, system_clock_source_dfll_config::quick_lock, system_clock_source_dpll_config::reference_clock, system_clock_source_dpll_config::reference_divider, system_clock_source_dpll_config::reference_frequency, system_clock_source_dfll_config::run_in_stanby, system_clock_source_xosc_config::run_in_standby, system_clock_source_xosc32k_config::run_in_standby, system_clock_source_osc32k_config::run_in_standby, system_clock_source_dpll_config::run_in_standby, system_gclk_chan_config::source_generator, system_clock_source_dfll_config::stable_tracking, system_clock_source_xosc32k_config::startup_time, system_clock_source_osc32k_config::startup_time, system_clock_source_xosc_config::startup_time, system_backup_clock_set_divider(), SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE, SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED, SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE, SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK, SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE, SYSTEM_CLOCK_SOURCE_DFLL, system_clock_source_dfll_get_config_defaults(), system_clock_source_dfll_set_config(), SYSTEM_CLOCK_SOURCE_DPLL, system_clock_source_dpll_get_config_defaults(), SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC, SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K, system_clock_source_dpll_set_config(), system_clock_source_enable(), system_clock_source_is_ready(), SYSTEM_CLOCK_SOURCE_OSC32K, system_clock_source_osc32k_get_config_defaults(), system_clock_source_osc32k_set_config(), SYSTEM_CLOCK_SOURCE_XOSC, SYSTEM_CLOCK_SOURCE_XOSC32K, system_clock_source_xosc32k_get_config_defaults(), system_clock_source_xosc32k_set_config(), system_clock_source_xosc_get_config_defaults(), system_clock_source_xosc_set_config(), system_cpu_clock_get_hz(), system_cpu_clock_set_divider(), system_flash_set_waitstates(), system_gclk_chan_enable(), system_gclk_chan_get_config_defaults(), system_gclk_chan_set_config(), system_gclk_init(), system_low_power_clock_set_divider(), SYSTEM_MAIN_CLOCK_DIV_1, SYSTEM_MAIN_CLOCK_DIV_8, system_main_clock_set_failure_detect(), SYSTEM_OSC16M_4M, SYSTEM_PERFORMANCE_LEVEL_0, SYSTEM_PERFORMANCE_LEVEL_2, system_switch_performance_level(), system_clock_source_dpll_config::wake_up_fast, and system_clock_source_dfll_config::wakeup_lock.

Referenced by system_init().

static void system_clock_source_dfll_get_config_defaults ( struct system_clock_source_dfll_config *const  config)
inlinestatic

Retrieve the default configuration for DFLL.

Fills a configuration structure with the default configuration for a DFLL oscillator module:

  • Open loop mode
  • QuickLock mode enabled
  • Chill cycle enabled
  • Output frequency lock maintained during device wake-up
  • Continuous tracking of the output frequency
  • Default tracking values at the mid-points for both coarse and fine tracking parameters
  • Don't run in STANDBY sleep mode
  • Run only when requested by peripheral (on demand)
Parameters
[out]configConfiguration structure to fill with default values

References Assert, system_clock_source_dfll_config::chill_cycle, system_clock_source_dfll_config::coarse_max_step, system_clock_source_dfll_config::coarse_value, system_clock_source_dfll_config::fine_max_step, system_clock_source_dfll_config::fine_value, system_clock_source_dfll_config::loop_mode, system_clock_source_dfll_config::multiply_factor, system_clock_source_dfll_config::on_demand, system_clock_source_dfll_config::quick_lock, system_clock_source_dfll_config::run_in_stanby, system_clock_source_dfll_config::stable_tracking, SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, and system_clock_source_dfll_config::wakeup_lock.

Referenced by system_clock_init().

enum status_code system_clock_source_disable ( const enum system_clock_source  clock_source)

Disables a clock source.

Disables a clock source that was previously enabled.

Parameters
[in]clock_sourceClock source to disable
Return values
STATUS_OKClock source was disabled successfully
STATUS_ERR_INVALID_ARGAn invalid or unavailable clock source was given

References Assert, _system_clock_dfll_config::control, _system_clock_module::dfll, STATUS_ERR_INVALID_ARG, STATUS_OK, SYSTEM_CLOCK_SOURCE_DFLL, SYSTEM_CLOCK_SOURCE_DPLL, SYSTEM_CLOCK_SOURCE_OSC16M, SYSTEM_CLOCK_SOURCE_OSC32K, SYSTEM_CLOCK_SOURCE_ULP32K, SYSTEM_CLOCK_SOURCE_XOSC, and SYSTEM_CLOCK_SOURCE_XOSC32K.

Referenced by _system_clock_source_osc16m_freq_sel().

static void system_clock_source_dpll_get_config_defaults ( struct system_clock_source_dpll_config *const  config)
inlinestatic

Retrieve the default configuration for DPLL.

Fills a configuration structure with the default configuration for a DPLL oscillator module:

  • Run only when requested by peripheral (on demand)
  • Don't run in STANDBY sleep mode
  • Lock bypass disabled
  • Fast wake up disabled
  • Low power mode disabled
  • Output frequency is 48MHz
  • Reference clock frequency is 32768Hz
  • Not divide reference clock
  • Select REF0 as reference clock
  • Set lock time to default mode
  • Use default filter
Parameters
[out]configConfiguration structure to fill with default values

References system_clock_source_dpll_config::filter, system_clock_source_dpll_config::lock_bypass, system_clock_source_dpll_config::lock_time, system_clock_source_dpll_config::low_power_enable, system_clock_source_dpll_config::on_demand, system_clock_source_dpll_config::output_frequency, system_clock_source_dpll_config::prescaler, system_clock_source_dpll_config::reference_clock, system_clock_source_dpll_config::reference_divider, system_clock_source_dpll_config::reference_frequency, system_clock_source_dpll_config::run_in_standby, SYSTEM_CLOCK_SOURCE_DPLL_DIV_1, SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, and system_clock_source_dpll_config::wake_up_fast.

Referenced by system_clock_init().

void system_clock_source_dpll_set_config ( struct system_clock_source_dpll_config *const  config)
enum status_code system_clock_source_enable ( const enum system_clock_source  system_clock_source)
bool system_clock_source_is_ready ( const enum system_clock_source  clock_source)

Checks if a clock source is ready.

Checks if a given clock source is ready to be used.

Parameters
[in]clock_sourceClock source to check if ready
Returns
Ready state of the given clock source.
Return values
trueClock source is enabled and ready
falseClock source is disabled or not yet ready

References CONF_CLOCK_DFLL_LOOP_MODE, SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED, SYSTEM_CLOCK_SOURCE_DFLL, SYSTEM_CLOCK_SOURCE_DPLL, SYSTEM_CLOCK_SOURCE_OSC16M, SYSTEM_CLOCK_SOURCE_OSC32K, SYSTEM_CLOCK_SOURCE_ULP32K, SYSTEM_CLOCK_SOURCE_XOSC, and SYSTEM_CLOCK_SOURCE_XOSC32K.

Referenced by _system_clock_source_osc16m_freq_sel(), and system_clock_init().

static void system_clock_source_osc16m_get_config_defaults ( struct system_clock_source_osc16m_config *const  config)
inlinestatic

Retrieve the default configuration for OSC16M.

Fills a configuration structure with the default configuration for an internal 16MHz (nominal) oscillator module:

  • Clock output frequency select 4MHz
  • Don't run in STANDBY sleep mode
  • Run only when requested by peripheral (on demand)
Parameters
[out]configConfiguration structure to fill with default values

References Assert, system_clock_source_osc16m_config::fsel, system_clock_source_osc16m_config::on_demand, system_clock_source_osc16m_config::run_in_standby, and SYSTEM_OSC16M_4M.

Referenced by _system_clock_source_osc16m_freq_sel().

void system_clock_source_osc16m_set_config ( struct system_clock_source_osc16m_config *const  config)

Configure the internal OSC16M oscillator clock source.

Configures the 16MHz (nominal) internal RC oscillator with the given configuration settings.

Note
Frequency selection can be done only when OSC16M is disabled.
Parameters
[in]configOSC16M configuration structure containing the new config

References system_clock_source_osc16m_config::fsel, system_clock_source_osc16m_config::on_demand, and system_clock_source_osc16m_config::run_in_standby.

Referenced by _system_clock_source_osc16m_freq_sel().

static void system_clock_source_osc32k_get_config_defaults ( struct system_clock_source_osc32k_config *const  config)
inlinestatic

Retrieve the default configuration for OSC32K.

Fills a configuration structure with the default configuration for an internal 32KHz oscillator module:

  • 1KHz clock output enabled
  • 32KHz clock output enabled
  • Don't run in STANDBY sleep mode
  • Run only when requested by peripheral (on demand)
  • Set start-up time to 130 cycles
  • Don't lock registers after configuration has been written
Parameters
[out]configConfiguration structure to fill with default values

References Assert, system_clock_source_osc32k_config::enable_1khz_output, system_clock_source_osc32k_config::enable_32khz_output, system_clock_source_osc32k_config::on_demand, system_clock_source_osc32k_config::run_in_standby, system_clock_source_osc32k_config::startup_time, SYSTEM_OSC32K_STARTUP_130, and system_clock_source_osc32k_config::write_once.

Referenced by system_clock_init().

void system_clock_source_osc32k_set_config ( struct system_clock_source_osc32k_config *const  config)

Configure the internal OSC32K oscillator clock source.

Configures the 32KHz (nominal) internal RC oscillator with the given configuration settings.

Parameters
[in]configOSC32K configuration structure containing the new config

References system_clock_source_osc32k_config::enable_1khz_output, system_clock_source_osc32k_config::enable_32khz_output, system_clock_source_osc32k_config::on_demand, system_clock_source_osc32k_config::run_in_standby, system_clock_source_osc32k_config::startup_time, and system_clock_source_osc32k_config::write_once.

Referenced by system_clock_init().

static void system_clock_source_osculp32k_get_config_defaults ( struct system_clock_source_osculp32k_config *const  config)
inlinestatic

Retrieve the default configuration for OSCULP32K.

Fills a configuration structure with the default configuration for an internal Ultra Low Power 32KHz oscillator module:

  • 1KHz clock output enabled
  • 32KHz clock output enabled
Parameters
[out]configConfiguration structure to fill with default values

References Assert, and system_clock_source_osculp32k_config::write_once.

void system_clock_source_osculp32k_set_config ( struct system_clock_source_osculp32k_config *const  config)

Configure the internal OSCULP32K oscillator clock source.

Configures the Ultra Low Power 32KHz internal RC oscillator with the given configuration settings.

Note
The OSCULP32K is enabled by default after a Power On Reset (POR) and will always run except during POR.
Parameters
[in]configOSCULP32K configuration structure containing the new config

References system_clock_source_osculp32k_config::write_once.

enum status_code system_clock_source_write_calibration ( const enum system_clock_source  system_clock_source,
const uint16_t  calibration_value,
const uint8_t  freq_range 
)
static void system_clock_source_xosc32k_get_config_defaults ( struct system_clock_source_xosc32k_config *const  config)
inlinestatic

Retrieve the default configuration for XOSC32K.

Fills a configuration structure with the default configuration for an external 32KHz oscillator module:

  • External Crystal
  • Start-up time of 16384 external clock cycles
  • Automatic crystal gain control mode disabled
  • Frequency of 32.768KHz
  • 1KHz clock output disabled
  • 32KHz clock output enabled
  • Don't run in STANDBY sleep mode
  • Run only when requested by peripheral (on demand)
  • Don't lock registers after configuration has been written
Parameters
[out]configConfiguration structure to fill with default values

References Assert, system_clock_source_xosc32k_config::enable_1khz_output, system_clock_source_xosc32k_config::enable_32khz_output, system_clock_source_xosc32k_config::external_clock, system_clock_source_xosc32k_config::frequency, system_clock_source_xosc32k_config::on_demand, system_clock_source_xosc32k_config::run_in_standby, system_clock_source_xosc32k_config::startup_time, SYSTEM_CLOCK_EXTERNAL_CRYSTAL, SYSTEM_XOSC32K_STARTUP_16384, and system_clock_source_xosc32k_config::write_once.

Referenced by system_clock_init().

static void system_clock_source_xosc_get_config_defaults ( struct system_clock_source_xosc_config *const  config)
inlinestatic

Retrieve the default configuration for XOSC.

Fills a configuration structure with the default configuration for an external oscillator module:

  • External Crystal
  • Start-up time of 16384 external clock cycles
  • Automatic crystal gain control mode disabled
  • Frequency of 12MHz
  • Don't run in STANDBY sleep mode
  • Run when it's enabled (not on demand)
Parameters
[out]configConfiguration structure to fill with default values

References Assert, system_clock_source_xosc_config::auto_gain_control, system_clock_source_xosc_config::external_clock, system_clock_source_xosc_config::frequency, system_clock_source_xosc_config::on_demand, system_clock_source_xosc_config::run_in_standby, system_clock_source_xosc_config::startup_time, SYSTEM_CLOCK_EXTERNAL_CRYSTAL, and SYSTEM_XOSC_STARTUP_16384.

Referenced by system_clock_init().

void system_clock_source_xosc_set_config ( struct system_clock_source_xosc_config *const  config)

Configure the external oscillator clock source.

Configures the external oscillator clock source with the given configuration settings.

Parameters
[in]configExternal oscillator configuration structure containing the new config

References system_clock_source_xosc_config::auto_gain_control, system_clock_source_xosc_config::external_clock, _system_clock_xosc_config::frequency, system_clock_source_xosc_config::frequency, system_clock_source_xosc_config::on_demand, system_clock_source_xosc_config::run_in_standby, system_clock_source_xosc_config::startup_time, SYSTEM_CLOCK_EXTERNAL_CRYSTAL, and _system_clock_module::xosc.

Referenced by system_clock_init().

static uint32_t system_cpu_clock_get_hz ( void  )
inlinestatic

Retrieves the current frequency of the CPU core.

Retrieves the operating frequency of the CPU core, obtained from the main generic clock and the set CPU bus divider.

Returns
Current CPU frequency in Hz.

References GCLK_GENERATOR_0, and system_gclk_gen_get_hz().

Referenced by system_clock_init().

static void system_cpu_clock_set_divider ( const enum system_main_clock_div  divider)
inlinestatic

Set main CPU clock divider.

Sets the clock divider used on the main clock to provide the CPU clock.

Parameters
[in]dividerCPU clock divider

Referenced by system_clock_init().

static void system_flash_set_waitstates ( uint8_t  wait_states)
inlinestatic

Set flash controller wait states.

Will set the number of wait states that are used by the onboard flash memory. The number of wait states depend on both device supply voltage and CPU speed. The required number of wait states can be found in the electrical characteristics of the device.

Parameters
[in]wait_statesNumber of wait states to use for internal flash

References Assert.

Referenced by system_clock_init().

void system_gclk_chan_disable ( const uint8_t  channel)

Disables a Generic Clock that was previously enabled.

Stops the clock generation of a Generic Clock that was previously started via a call to system_gclk_chan_enable().

Parameters
[in]channelGeneric Clock channel to disable

References Assert, system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

Referenced by extint_nmi_set_config(), and system_gclk_chan_set_config().

void system_gclk_chan_enable ( const uint8_t  channel)

Enables a Generic Clock that was previously configured.

Starts the clock generation of a Generic Clock that was previously configured via a call to system_gclk_chan_set_config().

Parameters
[in]channelGeneric Clock channel to enable

References system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

Referenced by _system_extint_init(), extint_nmi_set_config(), system_clock_init(), and usb_init().

static void system_gclk_chan_get_config_defaults ( struct system_gclk_chan_config *const  config)
inlinestatic

Initializes a Generic Clock configuration structure to defaults.

Initializes a given Generic Clock configuration structure to a set of known default values. This function should be called on all new instances of these configuration structures before being modified by the user application.

The default configuration is as follows:

  • The clock is sourced from the Generic Clock Generator channel 0
  • The clock configuration will not be write-locked when set
Parameters
[out]configConfiguration structure to initialize to default values

References Assert, GCLK_GENERATOR_0, and system_gclk_chan_config::source_generator.

Referenced by _system_extint_init(), system_clock_init(), and usb_init().

uint32_t system_gclk_chan_get_hz ( const uint8_t  channel)

Retrieves the clock frequency of a Generic Clock channel.

Determines the clock frequency (in Hz) of a specified Generic Clock channel, used as a source to a device peripheral module.

Parameters
[in]channelGeneric Clock Channel index
Returns
The frequency of the generic clock channel, in Hz.

References system_gclk_gen_get_hz(), system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

Referenced by system_clock_source_get_hz().

bool system_gclk_chan_is_enabled ( const uint8_t  channel)

Determins if the specified Generic Clock channel is enabled.

Parameters
[in]channelGeneric Clock Channel index
Returns
The enabled status.
Return values
trueThe Generic Clock channel is enabled
falseThe Generic Clock channel is disabled

References system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

bool system_gclk_chan_is_locked ( const uint8_t  channel)

Determins if the specified Generic Clock channel is locked.

Parameters
[in]channelGeneric Clock Channel index
Returns
The lock status.
Return values
trueThe Generic Clock channel is locked
falseThe Generic Clock channel is not locked

References system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

void system_gclk_chan_lock ( const uint8_t  channel)

Locks a Generic Clock channel from further configuration writes.

Locks a generic clock channel from further configuration writes. It is only possible to unlock the channel configuration through a power on reset.

Parameters
[in]channelGeneric Clock channel to enable

References system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

void system_gclk_chan_set_config ( const uint8_t  channel,
struct system_gclk_chan_config *const  config 
)

Writes a Generic Clock configuration to the hardware module.

Writes out a given configuration of a Generic Clock configuration to the hardware module. If the clock is currently running, it will be stopped.

Note
Once called the clock will not be running; to start the clock, call system_gclk_chan_enable() after configuring a clock channel.
Parameters
[in]channelGeneric Clock channel to configure
[in]configConfiguration settings for the clock

References Assert, system_gclk_chan_config::source_generator, and system_gclk_chan_disable().

Referenced by _system_extint_init(), system_clock_init(), and usb_init().

void system_gclk_gen_disable ( const uint8_t  generator)

Disables a Generic Clock Generator that was previously enabled.

Stops the clock generation of a Generic Clock Generator that was previously started via a call to system_gclk_gen_enable().

Parameters
[in]generatorGeneric Clock Generator index to disable

References system_gclk_is_syncing(), system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

void system_gclk_gen_enable ( const uint8_t  generator)

Enables a Generic Clock Generator that was previously configured.

Starts the clock generation of a Generic Clock Generator that was previously configured via a call to system_gclk_gen_set_config().

Parameters
[in]generatorGeneric Clock Generator index to enable

References system_gclk_is_syncing(), system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

static void system_gclk_gen_get_config_defaults ( struct system_gclk_gen_config *const  config)
inlinestatic

Initializes a Generic Clock Generator configuration structure to defaults.

Initializes a given Generic Clock Generator configuration structure to a set of known default values. This function should be called on all new instances of these configuration structures before being modified by the user application.

The default configuration is:

  • The clock is generated undivided from the source frequency
  • The clock generator output is low when the generator is disabled
  • The input clock is sourced from input clock channel 0
  • The clock will be disabled during sleep
  • The clock output will not be routed to a physical GPIO pin
Parameters
[out]configConfiguration structure to initialize to default values

References Assert, system_gclk_gen_config::division_factor, system_gclk_gen_config::high_when_disabled, system_gclk_gen_config::output_enable, system_gclk_gen_config::run_in_standby, and system_gclk_gen_config::source_clock.

Referenced by _system_clock_source_osc16m_freq_sel().

uint32_t system_gclk_gen_get_hz ( const uint8_t  generator)

Retrieves the clock frequency of a Generic Clock generator.

Determines the clock frequency (in Hz) of a specified Generic Clock generator, used as a source to a Generic Clock Channel module.

Parameters
[in]generatorGeneric Clock Generator index
Returns
The frequency of the generic clock generator, in Hz.

References system_clock_source_get_hz(), system_gclk_is_syncing(), system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

Referenced by system_backup_clock_get_hz(), system_cpu_clock_get_hz(), system_gclk_chan_get_hz(), and system_low_power_clock_get_hz().

bool system_gclk_gen_is_enabled ( const uint8_t  generator)

Determins if the specified Generic Clock Generator is enabled.

Parameters
[in]generatorGeneric Clock Generator index to check
Returns
The enabled status.
Return values
trueThe Generic Clock Generator is enabled
falseThe Generic Clock Generator is disabled

References system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

Referenced by extint_chan_set_config(), and extint_nmi_set_config().

void system_gclk_gen_set_config ( const uint8_t  generator,
struct system_gclk_gen_config *const  config 
)

Writes a Generic Clock Generator configuration to the hardware module.

Writes out a given configuration of a Generic Clock Generator configuration to the hardware module.

Note
Changing the clock source on the fly (on a running generator) can take additional time if the clock source is configured to only run on-demand (ONDEMAND bit is set) and it is not currently running (no peripheral is requesting the clock source). In this case the GCLK will request the new clock while still keeping a request to the old clock source until the new clock source is ready.
This function will not start a generator that is not already running; to start the generator, call system_gclk_gen_enable() after configuring a generator.
Parameters
[in]generatorGeneric Clock Generator index to configure
[in]configConfiguration settings for the generator

References Assert, system_gclk_gen_config::division_factor, system_gclk_gen_config::high_when_disabled, system_gclk_gen_config::output_enable, system_gclk_gen_config::run_in_standby, system_gclk_gen_config::source_clock, system_gclk_is_syncing(), system_interrupt_enter_critical_section(), and system_interrupt_leave_critical_section().

Referenced by _system_clock_source_osc16m_freq_sel().

void system_gclk_init ( void  )

Initializes the GCLK driver.

Initializes the Generic Clock module, disabling and resetting all active Generic Clock Generators and Channels to their power-on default values.

References system_apb_clock_set_mask(), and SYSTEM_CLOCK_APB_APBA.

Referenced by system_clock_init().

static uint32_t system_low_power_clock_get_hz ( void  )
inlinestatic

Retrieves the current frequency of Low-Power clock.

Retrieves the operating frequency of Low-Power, obtained from Low-Power clock and the set Low-Power clock divider.

Returns
Current CPU frequency in Hz.

References GCLK_GENERATOR_0, and system_gclk_gen_get_hz().

static void system_low_power_clock_set_divider ( const enum system_main_clock_div  divider)
inlinestatic

Set Low-Power Clock divider.

Sets the clock divider used on the main clock to provide the CPU clock.

Parameters
[in]dividerCPU clock divider to set

Referenced by system_clock_init().

static void system_main_clock_set_failure_detect ( const bool  enable)
inlinestatic

Enable or disable the main clock failure detection.

This mechanism allows switching automatically the main clock to the safe RCSYS clock, when the main clock source is considered off.

This may happen for instance when an external crystal is selected as the clock source of the main clock and the crystal dies. The mechanism is to detect, during a RCSYS period, at least one rising edge of the main clock. If no rising edge is seen the clock is considered failed. As soon as the detector is enabled, the clock failure detector (CFD) will monitor the divided main clock. When a clock failure is detected, the main clock automatically switches to the RCSYS clock and the CFD interrupt is generated if enabled.

Note
The failure detect must be disabled if the system clock is the same or slower than 32KHz as it will believe the system clock has failed with a too slow clock.
Parameters
[in]enableBoolean true to enable, false to disable detection

Referenced by system_clock_init().