Chip-specific system clock manager configuration.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_PLL1_DIV 2 /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
#define | CONFIG_PLL1_MUL 8 /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
#define | CONFIG_PLL1_SOURCE PLL_SRC_OSC0 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0 |
#define | CONFIG_USBCLK_DIV 1 /* Fusb = Fsys/(2 ^ USB_div) */ |
#define | CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 |
#define CONFIG_PLL1_DIV 2 /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL1_MUL 8 /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL1_SOURCE PLL_SRC_OSC0 |
Referenced by pll_enable_config_defaults().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0 |
Referenced by sysclk_init().
#define CONFIG_USBCLK_DIV 1 /* Fusb = Fsys/(2 ^ USB_div) */ |
Referenced by sysclk_enable_usb().
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 |
Referenced by sysclk_enable_usb().