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These macros give access to IP properties
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| #define | udd_get_endpoint_max_nbr() otg_get_max_nbr_endpoints() |
| | Get maximal number of endpoints. More...
|
| |
| #define | UDD_MAX_PEP_NB (USBC_EPT_NBR-1) |
| |
| #define | UDD_PEP_NB (USBC_EPT_NBR) |
| |
|
| #define | udd_low_speed_enable() USBC_SET_BITS(UDCON,LS) |
| | Enable/disable device low-speed mode. More...
|
| |
| #define | udd_low_speed_disable() USBC_CLR_BITS(UDCON,LS) |
| |
| #define | Is_udd_low_speed_enable() USBC_TST_BITS(UDCON,LS) |
| | Test if device low-speed mode is forced. More...
|
| |
| #define | udd_high_speed_enable() do { } while (0) |
| |
| #define | udd_high_speed_disable() do { } while (0) |
| |
| #define | Is_udd_full_speed_mode() true |
| |
|
| #define | udd_enable_hs_test_mode() do { } while (0) |
| |
| #define | udd_enable_hs_test_mode_j() do { } while (0) |
| |
| #define | udd_enable_hs_test_mode_k() do { } while (0) |
| |
| #define | udd_enable_hs_test_mode_packet() do { } while (0) |
| |
|
These macros manage the USBC Device attach.
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| #define | udd_detach_device() USBC_SET_BITS(UDCON,DETACH) |
| | detaches from USB bus More...
|
| |
| #define | udd_attach_device() USBC_CLR_BITS(UDCON,DETACH) |
| | attaches to USB bus More...
|
| |
| #define | Is_udd_detached() USBC_TST_BITS(UDCON,DETACH) |
| | test if the device is detached More...
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| |
|
These macros manage the USBC Device bus events.
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| #define | udd_initiate_remote_wake_up() USBC_SET_BITS(UDCON,RMWKUP) |
| | Initiates a remote wake-up event. More...
|
| |
| #define | Is_udd_pending_remote_wake_up() USBC_TST_BITS(UDCON,RMWKUP) |
| |
|
| #define | udd_enable_remote_wake_up_interrupt() USBC_REG_SET(UDINTE,UPRSME) |
| | Manage upstream resume event (=remote wakeup from device) The USB driver sends a resume signal called "Upstream Resume". More...
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| |
| #define | udd_disable_remote_wake_up_interrupt() USBC_REG_CLR(UDINTE,UPRSME) |
| |
| #define | Is_udd_remote_wake_up_interrupt_enabled() USBC_TST_BITS(UDINTE,UPRSME) |
| |
| #define | udd_ack_remote_wake_up_start() USBC_REG_CLR(UDINT,UPRSM) |
| |
| #define | udd_raise_remote_wake_up_start() USBC_REG_SET(UDINT,UPRSM) |
| |
| #define | Is_udd_remote_wake_up_start() USBC_TST_BITS(UDINT,UPRSM) |
| |
|
| #define | udd_enable_resume_interrupt() USBC_REG_SET(UDINTE,EORSME) |
| | Manage end of resume event (=remote wakeup from host) The USB controller detects a valid "End of Resume" signal initiated by the host. More...
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| |
| #define | udd_disable_resume_interrupt() USBC_REG_CLR(UDINTE,EORSME) |
| |
| #define | Is_udd_resume_interrupt_enabled() USBC_TST_BITS(UDINTE,EORSME) |
| |
| #define | udd_ack_resume() USBC_REG_CLR(UDINT,EORSM) |
| |
| #define | udd_raise_resume() USBC_REG_SET(UDINT,EORSM) |
| |
| #define | Is_udd_resume() USBC_TST_BITS(UDINT,EORSM) |
| |
|
| #define | udd_enable_wake_up_interrupt() USBC_REG_SET(UDINTE,WAKEUPE) |
| | Manage wake-up event (=usb line activity) The USB controller is reactivated by a filtered non-idle signal from the lines. More...
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| |
| #define | udd_disable_wake_up_interrupt() USBC_REG_CLR(UDINTE,WAKEUPE) |
| |
| #define | Is_udd_wake_up_interrupt_enabled() USBC_TST_BITS(UDINTE,WAKEUPE) |
| |
| #define | udd_ack_wake_up() USBC_REG_CLR(UDINT,WAKEUP) |
| |
| #define | udd_raise_wake_up() USBC_REG_SET(UDINT,WAKEUP) |
| |
| #define | Is_udd_wake_up() USBC_TST_BITS(UDINT,WAKEUP) |
| |
|
| #define | udd_enable_reset_interrupt() USBC_REG_SET(UDINTE,EORSTE) |
| | Manage reset event Set when a USB "End of Reset" has been detected. More...
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| |
| #define | udd_disable_reset_interrupt() USBC_REG_CLR(UDINTE,EORSTE) |
| |
| #define | Is_udd_reset_interrupt_enabled() USBC_TST_BITS(UDINTE,EORSTE) |
| |
| #define | udd_ack_reset() USBC_REG_CLR(UDINT,EORST) |
| |
| #define | udd_raise_reset() USBC_REG_SET(UDINT,EORST) |
| |
| #define | Is_udd_reset() USBC_TST_BITS(UDINT,EORST) |
| |
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| #define | udd_enable_sof_interrupt() USBC_REG_SET(UDINTE,SOFE) |
| | Manage start of frame event. More...
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| |
| #define | udd_disable_sof_interrupt() USBC_REG_CLR(UDINTE,SOFE) |
| |
| #define | Is_udd_sof_interrupt_enabled() USBC_TST_BITS(UDINTE,SOFE) |
| |
| #define | udd_ack_sof() USBC_REG_CLR(UDINT,SOF) |
| |
| #define | udd_raise_sof() USBC_REG_SET(UDINT,SOF) |
| |
| #define | Is_udd_sof() USBC_TST_BITS(UDINT,SOF) |
| |
| #define | udd_frame_number() USBC_RD_BITFIELD(UDFNUM,FNUM) |
| |
| #define | Is_udd_frame_number_crc_error() USBC_TST_BITS(UDFNUM,FNCERR) |
| |
|
| #define | udd_enable_msof_interrupt() do { } while(0) |
| | Manage Micro start of frame event (High Speed Only) More...
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| |
| #define | udd_disable_msof_interrupt() do { } while(0) |
| |
| #define | Is_udd_msof_interrupt_enabled() false |
| |
| #define | udd_ack_msof() do { } while(0) |
| |
| #define | udd_raise_msof() do { } while(0) |
| |
| #define | Is_udd_msof() false |
| |
| #define | udd_micro_frame_number() (Rd_bits(USBC->USBC_UDFNUM, USBC_UDFNUM_FNUM_Msk)) |
| |
|
| #define | udd_enable_suspend_interrupt() USBC_REG_SET(UDINTE,SUSPE) |
| | Manage suspend event. More...
|
| |
| #define | udd_disable_suspend_interrupt() USBC_REG_CLR(UDINTE,SUSPE) |
| |
| #define | Is_udd_suspend_interrupt_enabled() USBC_TST_BITS(UDINTE,SUSPE) |
| |
| #define | udd_ack_suspend() USBC_REG_CLR(UDINT,SUSP) |
| |
| #define | udd_raise_suspend() USBC_REG_SET(UDINT,SUSP) |
| |
| #define | Is_udd_suspend() USBC_TST_BITS(UDINT,SUSP) |
| |
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These macros manage the USBC Device address.
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| #define | udd_enable_address() USBC_SET_BITS(UDCON,ADDEN) |
| |
| #define | udd_disable_address() USBC_CLR_BITS(UDCON,ADDEN) |
| |
| #define | Is_udd_address_enabled() USBC_TST_BITS(UDCON,ADDEN) |
| |
| #define | udd_configure_address(addr) USBC_WR_BITFIELD(UDCON,UADD,addr) |
| |
| #define | udd_get_configured_address() USBC_RD_BITFIELD(UDCON,UADD) |
| |
|
These macros manage the common features of the endpoints.
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| #define | USBC_ARRAY(reg, index) (((volatile uint32_t*)(&USBC->TPASTE2(USBC_,reg)))[index]) |
| | Generic macro for USBC registers that can be arrayed. More...
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| |
| #define | USBC_EP_CLR_BITS(reg, bit, ep) |
| |
| #define | USBC_EP_SET_BITS(reg, bit, ep) |
| |
| #define | USBC_EP_TST_BITS(reg, bit, ep) |
| |
| #define | USBC_EP_RD_BITS(reg, bit, ep) |
| |
| #define | USBC_EP_WR_BITS(reg, bit, ep, value) |
| |
| #define | USBC_EP_RD_BITFIELD(reg, bit, ep) |
| |
| #define | USBC_EP_WR_BITFIELD(reg, bit, ep, value) |
| |
| #define | USBC_EP_REG_CLR(reg, bit, ep) |
| |
| #define | USBC_EP_REG_SET(reg, bit, ep) |
| |
|
| #define | udd_disable_endpoints() (Clr_bits(USBC->USBC_UERST, (1 << USBC_EPT_NBR) - 1)) |
| |
| #define | udd_enable_endpoint(ep) (Set_bits(USBC->USBC_UERST, USBC_UERST_EPEN0 << (ep))) |
| |
| #define | udd_disable_endpoint(ep) (Clr_bits(USBC->USBC_UERST, USBC_UERST_EPEN0 << (ep))) |
| |
| #define | Is_udd_endpoint_enabled(ep) (Tst_bits(USBC->USBC_UERST, USBC_UERST_EPEN0 << (ep))) |
| |
| #define | udd_reset_endpoint(ep) |
| |
| #define | Is_udd_resetting_endpoint(ep) (!Is_udd_endpoint_enabled()) |
| |
| #define | udd_configure_endpoint_type(ep, type) USBC_EP_WR_BITS(UECFG,EPTYPE,ep,type) |
| |
| #define | udd_get_endpoint_type(ep) USBC_EP_RD_BITS(UECFG,EPTYPE,ep) |
| |
| #define | Is_udd_endpoint_type_control(ep) (USBC_EP_RD_BITS(UECFG,EPTYPE,ep) == USBC_UECFG0_EPTYPE_CONTROL) |
| |
| #define | Is_udd_endpoint_type_bulk(ep) (USBC_EP_RD_BITS(UECFG,EPTYPE,ep) == USBC_UECFG0_EPTYPE_BULK) |
| |
| #define | Is_udd_endpoint_type_iso(ep) (USBC_EP_RD_BITS(UECFG,EPTYPE,ep) == USBC_UECFG0_EPTYPE_ISOCHRONOUS) |
| |
| #define | Is_udd_endpoint_type_int(ep) (USBC_EP_RD_BITS(UECFG,EPTYPE,ep) == USBC_UECFG0_EPTYPE_INTERRUPT) |
| |
| #define | udd_configure_endpoint_direction(ep, dir) USBC_EP_WR_BITS(UECFG,EPDIR,ep,dir) |
| |
| #define | udd_get_endpoint_direction(ep) USBC_EP_RD_BITS(UECFG,EPDIR,ep) |
| |
| #define | Is_udd_endpoint_in(ep) USBC_EP_TST_BITS(UECFG,EPDIR,ep) |
| |
| #define | udd_format_endpoint_size(size) (32 - clz(((uint32_t)Min(Max(size, 8), 1024) << 1) - 1) - 1 - 3) |
| | Bounds given integer size to allowed range and rounds it up to the nearest available greater size, then applies register format of USBC controller for endpoint size bit-field. More...
|
| |
| #define | udd_configure_endpoint_size(ep, size) (USBC_EP_WR_BITFIELD(UECFG,EPSIZE,ep,udd_format_endpoint_size(size))) |
| |
| #define | udd_get_endpoint_size(ep) (8 << USBC_EP_RD_BITFIELD(UECFG,EPSIZE,ep)) |
| |
| #define | udd_configure_endpoint_bank(ep, bank) USBC_EP_WR_BITS(UECFG,EPBK,ep,bank) |
| |
| #define | udd_get_endpoint_bank(ep) USBC_EP_RD_BITS(UECFG,EPBK,ep) |
| |
| #define | udd_configure_endpoint(ep, type, dir, size, bank) |
| | configures selected endpoint in one step More...
|
| |
| #define | udd_reset_data_toggle(ep) USBC_EP_REG_SET(UECON,RSTDT,ep) |
| |
| #define | Is_udd_data_toggle_reset(ep) USBC_EP_TST_BITS(UECON,RSTDT,ep) |
| |
| #define | udd_data_toggle(ep) USBC_EP_RD_BITFIELD(UESTA,DTSEQ,ep) |
| |
|
| #define | udd_enable_global_nak() USBC_SET_BITS(UDCON,GNAK) |
| |
| #define | udd_disable_global_nak() USBC_CLR_BITS(UDCON,GNAK) |
| |
| #define | Is_udd_global_nak_enabled() USBC_TST_BITS(UDCON,GNAK) |
| |
|
These macros control the endpoints interrupts.
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| #define | udd_enable_endpoint_interrupt(ep) (USBC->USBC_UDINTESET = USBC_UDINTESET_EP0INTES << (ep)) |
| |
| #define | udd_disable_endpoint_interrupt(ep) (USBC->USBC_UDINTECLR = USBC_UDINTECLR_EP0INTEC << (ep)) |
| |
| #define | Is_udd_endpoint_interrupt_enabled(ep) (Tst_bits(USBC->USBC_UDINTE, USBC_UDINTE_EP0INTE << (ep))) |
| |
| #define | Is_udd_endpoint_interrupt(ep) (Tst_bits(USBC->USBC_UDINT, USBC_UDINT_EP0INT << (ep))) |
| |
| #define | udd_get_interrupt_endpoint_number() |
| |
| #define | USBC_UDINT_EP0INT_Pos 12 |
| |
|
These macros control the endpoint errors.
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| #define | udd_enable_stall_handshake(ep) USBC_EP_REG_SET(UECON,STALLRQ,ep) |
| | enables the STALL handshake More...
|
| |
| #define | udd_disable_stall_handshake(ep) USBC_EP_REG_CLR(UECON,STALLRQ,ep) |
| | disables the STALL handshake More...
|
| |
| #define | Is_udd_endpoint_stall_requested(ep) USBC_EP_TST_BITS(UECON,STALLRQ,ep) |
| | tests if STALL handshake request is running More...
|
| |
| #define | Is_udd_stall(ep) USBC_EP_TST_BITS(UESTA,STALLEDI,ep) |
| | tests if STALL sent More...
|
| |
| #define | udd_ack_stall(ep) USBC_EP_REG_CLR(UESTA,STALLEDI,ep) |
| | acks STALL sent More...
|
| |
| #define | udd_raise_stall(ep) USBC_EP_REG_SET(UESTA,STALLEDI,ep) |
| | raises STALL sent More...
|
| |
| #define | udd_enable_stall_interrupt(ep) USBC_EP_REG_SET(UECON,STALLEDE,ep) |
| | enables STALL sent interrupt More...
|
| |
| #define | udd_disable_stall_interrupt(ep) USBC_EP_REG_CLR(UECON,STALLEDE,ep) |
| | disables STALL sent interrupt More...
|
| |
| #define | Is_udd_stall_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,STALLEDE,ep) |
| | tests if STALL sent interrupt is enabled More...
|
| |
| #define | Is_udd_ram_access_error(ep) USBC_EP_TST_BITS(UESTA,RAMACCERI,ep) |
| | tests if a RAM access error occur More...
|
| |
| #define | Is_udd_nak_out(ep) USBC_EP_TST_BITS(UESTA,NAKOUTI,ep) |
| | tests if NAK OUT received More...
|
| |
| #define | udd_ack_nak_out(ep) USBC_EP_REG_CLR(UESTA,NAKOUTI,ep) |
| | acks NAK OUT received More...
|
| |
| #define | udd_raise_nak_out(ep) USBC_EP_REG_SET(UESTA,NAKOUTI,ep) |
| | raises NAK OUT received More...
|
| |
| #define | udd_enable_nak_out_interrupt(ep) USBC_EP_REG_SET(UECON,NAKOUTE,ep) |
| | enables NAK OUT interrupt More...
|
| |
| #define | udd_disable_nak_out_interrupt(ep) USBC_EP_REG_CLR(UECON,NAKOUTE,ep) |
| | disables NAK OUT interrupt More...
|
| |
| #define | Is_udd_nak_out_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,NAKOUTE,ep) |
| | tests if NAK OUT interrupt is enabled More...
|
| |
| #define | Is_udd_nak_in(ep) USBC_EP_TST_BITS(UESTA,NAKINI,ep) |
| | tests if NAK IN received More...
|
| |
| #define | udd_ack_nak_in(ep) USBC_EP_REG_CLR(UESTA,NAKINI,ep) |
| | acks NAK IN received More...
|
| |
| #define | udd_raise_nak_in(ep) USBC_EP_REG_SET(UESTA,NAKINI,ep) |
| | raises NAK IN received More...
|
| |
| #define | udd_enable_nak_in_interrupt(ep) USBC_EP_REG_SET(UECON,NAKINE,ep) |
| | enables NAK IN interrupt More...
|
| |
| #define | udd_disable_nak_in_interrupt(ep) USBC_EP_REG_CLR(UECON,NAKINE,ep) |
| | disables NAK IN interrupt More...
|
| |
| #define | Is_udd_nak_in_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,NAKINE,ep) |
| | tests if NAK IN interrupt is enabled More...
|
| |
| #define | udd_ack_overflow_interrupt(ep) USBC_EP_REG_CLR(UESTA,OVERFI,ep) |
| | acks endpoint isochronous overflow interrupt More...
|
| |
| #define | udd_raise_overflow_interrupt(ep) USBC_EP_REG_SET(UESTA,OVERFI,ep) |
| | raises endpoint isochronous overflow interrupt More...
|
| |
| #define | Is_udd_overflow(ep) USBC_EP_TST_BITS(UESTA,OVERFI,ep) |
| | tests if an overflow occurs More...
|
| |
| #define | udd_enable_overflow_interrupt(ep) USBC_EP_REG_SET(UECON,OVERFE,ep) |
| | enables overflow interrupt More...
|
| |
| #define | udd_disable_overflow_interrupt(ep) USBC_EP_REG_CLR(UECON,OVERFE,ep) |
| | disables overflow interrupt More...
|
| |
| #define | Is_udd_overflow_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,OVERFE,ep) |
| | tests if overflow interrupt is enabled More...
|
| |
| #define | udd_ack_underflow_interrupt(ep) USBC_EP_REG_CLR(UESTA,UNDERFI,ep) |
| | acks endpoint isochronous underflow interrupt More...
|
| |
| #define | udd_raise_underflow_interrupt(ep) USBC_EP_REG_SET(UESTA,UNDERFI,ep) |
| | raises endpoint isochronous underflow interrupt More...
|
| |
| #define | Is_udd_underflow(ep) USBC_EP_TST_BITS(UESTA,UNDERFI,ep) |
| | tests if an underflow occurs More...
|
| |
| #define | udd_enable_underflow_interrupt(ep) USBC_EP_REG_SET(UECON,RXSTPE,ep) |
| | enables underflow interrupt More...
|
| |
| #define | udd_disable_underflow_interrupt(ep) USBC_EP_REG_CLR(UECON,RXSTPE,ep) |
| | disables underflow interrupt More...
|
| |
| #define | Is_udd_underflow_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,RXSTPE,ep) |
| | tests if underflow interrupt is enabled More...
|
| |
| #define | Is_udd_crc_error(ep) USBC_EP_TST_BITS(UESTA,STALLEDI,ep) |
| | tests if CRC ERROR ISO OUT detected More...
|
| |
| #define | udd_ack_crc_error(ep) USBC_EP_REG_CLR(UESTA,STALLEDI,ep) |
| | acks CRC ERROR ISO OUT detected More...
|
| |
| #define | udd_raise_crc_error(ep) USBC_EP_REG_SET(UESTA,STALLEDI,ep) |
| | raises CRC ERROR ISO OUT detected More...
|
| |
| #define | udd_enable_crc_error_interrupt(ep) USBC_EP_REG_SET(UECON,STALLEDE,ep) |
| | enables CRC ERROR ISO OUT detected interrupt More...
|
| |
| #define | udd_disable_crc_error_interrupt(ep) USBC_EP_REG_CLR(UECON,STALLEDE,ep) |
| | disables CRC ERROR ISO OUT detected interrupt More...
|
| |
| #define | Is_udd_crc_error_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,STALLEDE,ep) |
| | tests if CRC ERROR ISO OUT detected interrupt is enabled More...
|
| |
|
These macros control the endpoint banks.
|
| #define | udd_ack_fifocon(ep) USBC_EP_REG_CLR(UECON,FIFOCON,ep) |
| |
| #define | Is_udd_fifocon(ep) USBC_EP_TST_BITS(UECON,FIFOCON,ep) |
| |
| #define | udd_disable_nyet(ep) USBC_EP_REG_SET(UECON,NYETDIS,ep) |
| |
| #define | udd_enable_nyet(ep) USBC_EP_REG_CLR(UECON,NYETDIS,ep) |
| |
| #define | udd_enable_busy_bank0(ep) USBC_EP_REG_SET(UECON,BUSY0,ep) |
| |
| #define | udd_disable_busy_bank0(ep) USBC_EP_REG_CLR(UECON,BUSY0,ep) |
| |
| #define | udd_enable_busy_bank1(ep) USBC_EP_REG_SET(UECON,BUSY1,ep) |
| |
| #define | udd_disable_busy_bank1(ep) USBC_EP_REG_CLR(UECON,BUSY1,ep) |
| |
| #define | udd_nb_busy_bank(ep) USBC_EP_RD_BITFIELD(UESTA,NBUSYBK,ep) |
| |
| #define | udd_current_bank(ep) USBC_EP_RD_BITFIELD(UESTA,CURRBK,ep) |
| |
| #define | udd_kill_last_in_bank(ep) USBC_EP_REG_SET(UECON,KILLBK,ep) |
| |
| #define | Is_udd_last_in_bank_killed(ep) USBC_EP_TST_BITS(UECON,KILLBK,ep) |
| |
| #define | udd_force_bank_interrupt(ep) USBC_EP_REG_SET(UESTA,NBUSYBK,ep) |
| |
| #define | udd_unforce_bank_interrupt(ep) USBC_EP_REG_SET(UESTA,NBUSYBK,ep) |
| |
| #define | udd_enable_bank_interrupt(ep) USBC_EP_REG_SET(UECON,NBUSYBKE,ep) |
| |
| #define | udd_disable_bank_interrupt(ep) USBC_EP_REG_CLR(UECON,NBUSYBKE,ep) |
| |
| #define | Is_udd_bank_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,NBUSYBKE,ep) |
| |
| #define | Is_udd_short_packet(ep) USBC_EP_TST_BITS(UESTA,SHORTPACKETI,ep) |
| |
| #define | udd_ack_short_packet(ep) USBC_EP_REG_CLR(UESTA,SHORTPACKETI,ep) |
| |
| #define | udd_raise_short_packet(ep) USBC_EP_REG_SET(UESTA,SHORTPACKETI,ep) |
| |
| #define | udd_enable_short_packet_interrupt(ep) USBC_EP_REG_SET(UECON,SHORTPACKETE,ep) |
| |
| #define | udd_disable_short_packet_interrupt(ep) USBC_EP_REG_CLR(UECON,SHORTPACKETE,ep) |
| |
| #define | Is_udd_short_packet_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,SHORTPACKETE,ep) |
| |
|
These macros control the endpoint transfers.
|
| #define | Is_udd_setup_received(ep) USBC_EP_TST_BITS(UESTA,RXSTPI,ep) |
| |
| #define | udd_ack_setup_received(ep) USBC_EP_REG_CLR(UESTA,RXSTPI,ep) |
| |
| #define | udd_raise_setup_received(ep) USBC_EP_REG_SET(UESTA,RXSTPI,ep) |
| |
| #define | udd_enable_setup_received_interrupt(ep) USBC_EP_REG_SET(UECON,RXSTPE,ep) |
| |
| #define | udd_disable_setup_received_interrupt(ep) USBC_EP_REG_CLR(UECON,RXSTPE,ep) |
| |
| #define | Is_udd_setup_received_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,RXSTPE,ep) |
| |
| #define | Is_udd_out_received(ep) USBC_EP_TST_BITS(UESTA,RXOUTI,ep) |
| |
| #define | udd_ack_out_received(ep) USBC_EP_REG_CLR(UESTA,RXOUTI,ep) |
| |
| #define | udd_raise_out_received(ep) USBC_EP_REG_SET(UESTA,RXOUTI,ep) |
| |
| #define | udd_enable_out_received_interrupt(ep) USBC_EP_REG_SET(UECON,RXOUTE,ep) |
| |
| #define | udd_disable_out_received_interrupt(ep) USBC_EP_REG_CLR(UECON,RXOUTE,ep) |
| |
| #define | Is_udd_out_received_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,RXOUTE,ep) |
| |
| #define | Is_udd_in_send(ep) USBC_EP_TST_BITS(UESTA,TXINI,ep) |
| |
| #define | udd_ack_in_send(ep) USBC_EP_REG_CLR(UESTA,TXINI,ep) |
| |
| #define | udd_raise_in_send(ep) USBC_EP_REG_SET(UESTA,TXINI,ep) |
| |
| #define | udd_enable_in_send_interrupt(ep) USBC_EP_REG_SET(UECON,TXINE,ep) |
| |
| #define | udd_disable_in_send_interrupt(ep) USBC_EP_REG_CLR(UECON,TXINE,ep) |
| |
| #define | Is_udd_in_send_interrupt_enabled(ep) USBC_EP_TST_BITS(UECON,TXINE,ep) |
| |
|
| #define | udd_udesc_set_buf0_addr(ep, buf) udd_g_ep_table[ep*2].endpoint_pipe_address = buf |
| |
| #define | udd_udesc_rst_buf0_size(ep) udd_g_ep_table[ep*2].SIZES.multi_packet_size = 0 |
| |
| #define | udd_udesc_get_buf0_size(ep) udd_g_ep_table[ep*2].SIZES.multi_packet_size |
| |
| #define | udd_udesc_set_buf0_size(ep, size) udd_g_ep_table[ep*2].SIZES.multi_packet_size = size |
| |
| #define | udd_udesc_rst_buf0_ctn(ep) udd_g_ep_table[ep*2].SIZES.byte_count = 0 |
| |
| #define | udd_udesc_get_buf0_ctn(ep) udd_g_ep_table[ep*2].SIZES.byte_count |
| |
| #define | udd_udesc_set_buf0_ctn(ep, size) udd_g_ep_table[ep*2].SIZES.byte_count = size |
| |
| #define | udd_udesc_set_buf0_autozlp(ep, val) udd_g_ep_table[ep*2].SIZES.auto_zlp = val |
| |
| #define | UDD_ENDPOINT_MAX_TRANS ((32*1024)-1) |
| |
1.8.5