Chip-specific system clock manager configuration.
Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_PLL0_DIV 4 /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
#define | CONFIG_PLL0_MUL (192000000 / FOSC0) /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
#define | CONFIG_PLL0_SOURCE PLL_SRC_OSC0 |
#define | CONFIG_SYSCLK_CPU_DIV 0 |
#define | CONFIG_SYSCLK_PBA_DIV 0 |
#define | CONFIG_SYSCLK_PBB_DIV 0 |
#define | CONFIG_SYSCLK_PBC_DIV 0 |
#define | CONFIG_SYSCLK_PBD_DIV 0 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 |
#define | CONFIG_USBCLK_DIV 1 |
#define | CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 |
#define CONFIG_PLL0_DIV 4 /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_MUL (192000000 / FOSC0) /* Fpll = (Fclk * PLL_mul) / PLL_div */ |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0 |
Referenced by pll_enable_config_defaults().
#define CONFIG_SYSCLK_CPU_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBA_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBB_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBC_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBD_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 |
Referenced by sysclk_init().
#define CONFIG_USBCLK_DIV 1 |
Referenced by sysclk_enable_usb().
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 |
Referenced by sysclk_enable_usb().