Atmel Development Board Clock Configuration (ASF)
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
| #define | CONFIG_DFLL0_DIV (1) |
| #define | CONFIG_DFLL0_MUL (40000000 / BOARD_OSC32_HZ) |
| #define | CONFIG_DFLL0_SOURCE (GENCLK_SRC_OSC32K) |
| #define | CONFIG_SYSCLK_CPU_DIV (2) |
| #define | CONFIG_SYSCLK_PBA_DIV (2) |
| #define | CONFIG_SYSCLK_PBB_DIV (2) |
| #define | CONFIG_SYSCLK_PBC_DIV (2) |
| #define | CONFIG_SYSCLK_SOURCE (SYSCLK_SRC_DFLL) |
| #define CONFIG_DFLL0_DIV (1) |
Referenced by dfll_enable_config_defaults().
| #define CONFIG_DFLL0_MUL (40000000 / BOARD_OSC32_HZ) |
Referenced by dfll_enable_config_defaults().
| #define CONFIG_DFLL0_SOURCE (GENCLK_SRC_OSC32K) |
Referenced by dfll_enable_config_defaults().
| #define CONFIG_SYSCLK_CPU_DIV (2) |
Referenced by sysclk_init().
| #define CONFIG_SYSCLK_PBA_DIV (2) |
Referenced by sysclk_init().
| #define CONFIG_SYSCLK_PBB_DIV (2) |
Referenced by sysclk_init().
| #define CONFIG_SYSCLK_PBC_DIV (2) |
| #define CONFIG_SYSCLK_SOURCE (SYSCLK_SRC_DFLL) |
Referenced by sysclk_init().
1.8.5