In this use case the ADC module and one channel are configured for:
- 12-bit, unsigned conversions
- Internal bandgap as 3.3 V reference
- ADC clock rate of at most 6.4 MHz and maximum sample rate is 1 MHz
- Software triggering of conversions
- Comparison event happen and interrupt handling
- Single channel measurement
- ADC_CHANNEL_5 as positive input
Setup steps
Example code
Add to application C-file:
void ADC_IrqHandler(void)
{
{
}
}
Workflow
- Define the interrupt service handler in the application:
void ADC_IrqHandler(void)
{
{
}
}
- Note
- Get ADC status and check if comparison event occurred. If occurred, read the ADC channel value and comparison mode.
- Initialize the given ADC with the specified ADC clock and startup time:
- Note
- The ADC clock range is between master clock/2 and master clock/512. The function sysclk_get_main_hz() is used to get the master clock frequency while ADC_CLOCK gives the ADC clock frequency.
- Configure ADC timing:
- Note
- Tracking Time = (0 + 1) * ADC Clock period Settling Time = ADC_SETTLING_TIME_3 * ADC Clock period Transfer Time = (1 * 2 + 3) * ADC Clock period
- Set the ADC resolution.
- Note
- The resolution value can be set to 10 bits or 12 bits.
- Enable the specified ADC channel:
- Set the comparison ADC channel, mode and window:
- Note
- The high and low threshold of comparison window can be set by the user. An event will be generated whenever the converted data is in the comparison window.
- Enable ADC interrupts:
- Configure software conversion trigger:
Usage steps
Example code
Add to, e.g., main loop in application C-file:
Workflow
- Start ADC conversion on the configured channels: