Chip-specific system clock manager configuration.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_DFLL0_DIV 1 |
#define | CONFIG_DFLL0_FREQ 48000000UL |
#define | CONFIG_DFLL0_MUL (CONFIG_DFLL0_FREQ / BOARD_OSC32_HZ) |
#define | CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC32K |
#define | CONFIG_SYSCLK_CPU_DIV 0 |
#define | CONFIG_SYSCLK_PBA_DIV 0 |
#define | CONFIG_SYSCLK_PBB_DIV 0 |
#define | CONFIG_SYSCLK_PBC_DIV 0 |
#define | CONFIG_SYSCLK_PBD_DIV 0 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_DFLL |
#define CONFIG_DFLL0_DIV 1 |
Referenced by dfll_enable_config_defaults().
#define CONFIG_DFLL0_FREQ 48000000UL |
#define CONFIG_DFLL0_MUL (CONFIG_DFLL0_FREQ / BOARD_OSC32_HZ) |
Referenced by dfll_enable_config_defaults().
#define CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC32K |
Referenced by dfll_enable_config_defaults().
#define CONFIG_SYSCLK_CPU_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBA_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBB_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBC_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_PBD_DIV 0 |
Referenced by sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_DFLL |
Referenced by sysclk_init().