Quick Start Guide for SYSTEM CLOCK - Basic

In this case we apply the following configuration:

• RC8MHz (internal 8MHz RC oscillator)
  • Divide by four, giving a frequency of 2MHz
• DFLL (Digital frequency locked loop)
  • Open loop mode
  • 48MHz frequency
• CPU clock
  • Use two wait states when reading from flash memory
  • Use the DFLL, configured to 48MHz

Setup

Prerequisites

There are no special setup requirements for this use-case.

Code

Copy-paste the following setup code to your application:

void configure_osc32k(void)
{
    struct system_clock_source_xosc_config config_osc32k;
    system_clock_source_xosc32k_get_config_defaults(&config_osc32k);

    config_osc32k.startup_time = SYSTEM_XOSC_STARTUP_4096;

    system_clock_source_xosc_set_config(&config_osc32k);
}

Workflow

1. Create a EXTOSC32K module configuration struct, which can be filled out to adjust the configuration of the external 32KHz oscillator channel.

       struct system_clock_source_xosc32k_config config_ext32k;

2. Initialize the oscillator configuration struct with the module's default values.

       system_clock_source_xosc32k_get_config_defaults(&config_ext32k);

   Note

   This should always be performed before using the configuration struct to ensure that all values are initialized to known default settings.

3. Alter the EXTOSC32K module configuration struct to require a start-up time of 4096 clock cycles.

       config_ext32k.startup_time = SYSTEM_XOSC32K_STARTUP_4096;

4. Write the new configuration to the EXTOSC32K module.

       system_clock_source_xosc32k_set_config(&config_ext32k);

5. Create a DFLL module configuration struct, which can be filled out to adjust the configuration of the external 32KHz oscillator channel.

       struct system_clock_source_dfll_config config_dfll;

6. Initialize the DFLL oscillator configuration struct with the module's default values.

       system_clock_source_dfll_get_config_defaults(&config_dfll);

   Note

   This should always be performed before using the configuration struct to ensure that all values are initialized to known default settings.

7. Write the new configuration to the DFLL module.

       system_clock_source_dfll_set_config(&config_dfll);

Use Case

Code

Copy-paste the following code to your user application:

#if(SAMR30E)
{
  /* Configure the internal 32KHz oscillator */
  configure_osc32k();
  /* Enable the internal 32KHz oscillator */
  enum status_code osc32k_status =
  system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);

  if (osc32k_status != STATUS_OK) {
      /* Error enabling the clock source */
  }
}
    
#else
{
    /* Configure the external 32KHz oscillator */
    configure_extosc32k();
    /* Enable the external 32KHz oscillator */
    enum status_code osc32k_status =
            system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);

    if (osc32k_status != STATUS_OK) {
        /* Error enabling the clock source */
    }
}
#endif
#if (!SAMC21)
    /* Configure the DFLL in open loop mode using default values */
    configure_dfll_open_loop();

    /* Enable the DFLL oscillator */
    enum status_code dfll_status =
            system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);

    if (dfll_status != STATUS_OK) {
        /* Error enabling the clock source */
    }

    /* Configure flash wait states before switching to high frequency clock */
    system_flash_set_waitstates(2);

    /* Change system clock to DFLL */
    struct system_gclk_gen_config config_gclock_gen;
    system_gclk_gen_get_config_defaults(&config_gclock_gen);
    config_gclock_gen.source_clock    = SYSTEM_CLOCK_SOURCE_DFLL;
    config_gclock_gen.division_factor = 1;
    system_gclk_gen_set_config(GCLK_GENERATOR_0, &config_gclock_gen);
#endif

Workflow

1. Configure the external 32KHz oscillator source using the previously defined setup function.

       configure_extosc32k();

2. Enable the configured external 32KHz oscillator source.

       enum status_code osc32k_status =
               system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
   
       if (osc32k_status != STATUS_OK) {
           /* Error enabling the clock source */
       }

3. Configure the DFLL oscillator source using the previously defined setup function.

       configure_dfll_open_loop();

4. Enable the configured DFLL oscillator source.

       enum status_code dfll_status =
               system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
   
       if (dfll_status != STATUS_OK) {
           /* Error enabling the clock source */
       }

5. Configure the flash wait states to have two wait states per read, as the high speed DFLL will be used as the system clock. If insufficient wait states are used, the device may crash randomly due to misread instructions.

       system_flash_set_waitstates(2);

6. Switch the system clock source to the DFLL, by reconfiguring the main clock generator.

       struct system_gclk_gen_config config_gclock_gen;
       system_gclk_gen_get_config_defaults(&config_gclock_gen);
       config_gclock_gen.source_clock    = SYSTEM_CLOCK_SOURCE_DFLL;
       config_gclock_gen.division_factor = 1;
       system_gclk_gen_set_config(GCLK_GENERATOR_0, &config_gclock_gen);