Compiler abstraction layer and code utilities | Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices |
Status Codes | |
Preprocessor - Macro Recursion | |
Preprocessor - Macro Repeat | |
Preprocessor - Stringize | |
Preprocessor - Token Paste | |
Global interrupt management | This is a driver for global enabling and disabling of interrupts |
Deprecated interrupt definitions | |
Atmel part identification macros | This collection of macros identify which series and families that the various Atmel parts belong to |
AVR UC3 parts | |
AVR XMEGA parts | |
megaAVR parts | |
SAM parts | |
Generic board support | The generic board support module includes board-specific definitions and function prototypes, such as the board initialization function |
SAM L21 Xplained Pro board | |
Features | Symbols that describe features and capabilities of the board |
SAM Port (PORT) Driver | This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's General Purpose Input/Output (GPIO) pin functionality, for manual pin state reading and writing |
SAM System Pin Multiplexer (SYSTEM PINMUX) Driver | This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's physical I/O Pins, to alter the direction and input/drive characteristics as well as to configure the pin peripheral multiplexer selection |
SAM System (SYSTEM) Driver | This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's system relation functionality, necessary for the basic device operation |
SAM System Clock Management (SYSTEM CLOCK) Driver | This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's clocking related functions |
SAM System Interrupt (SYSTEM INTERRUPT) Driver | This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of internal software and hardware interrupts/exceptions |