Microchip® Advanced Software Framework

Macros | Typedefs | Enumerations
avr2025_mac/source/tal/at86rf233/inc/at86rf233.h File Reference
#include "tal_types.h"

Macros

#define AACK_SPC_DISABLE   (0)
 Constant AACK_SPC_DISABLE for sub-register SR_AACK_SPC_EN in register XAH_CTRL_1. More...
 
#define AACK_SPC_ENABLE   (1)
 Constant AACK_SPC_ENABLE for sub-register SR_AACK_SPC_EN in register XAH_CTRL_1. More...
 
#define ACK_DISABLE   (1)
 Constant ACK_DISABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1. More...
 
#define ACK_ENABLE   (0)
 Constant ACK_ENABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1. More...
 
#define ACK_TIME_12_SYMBOLS   (0)
 Constant ACK_TIME_12_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1. More...
 
#define ACK_TIME_2_SYMBOLS   (1)
 Constant ACK_TIME_2_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1. More...
 
#define AES_BASE_ADDR   (0x80)
 Base address for Transceiver AES address space. More...
 
#define AES_DIR_DECRYPT   (1)
 Constant AES_DIR_DECRYPT for sub-register SR_AES_DIR in register AES_CTRL. More...
 
#define AES_DIR_ENCRYPT   (0)
 Constant AES_DIR_ENCRYPT for sub-register SR_AES_DIR in register AES_CTRL. More...
 
#define AES_DONE   (1)
 Constant AES_DONE for sub-register SR_AES_DONE in register AES_STATUS. More...
 
#define AES_ERROR   (1)
 Constant AES_ERROR for sub-register SR_AES_ER in register AES_STATUS. More...
 
#define AES_MODE_CBC   (2)
 Constant AES_MODE_CBC for sub-register SR_AES_MODE in register AES_CTRL. More...
 
#define AES_MODE_ECB   (0)
 Constant AES_MODE_ECB for sub-register SR_AES_MODE in register AES_CTRL. More...
 
#define AES_MODE_KEY   (1)
 Constant AES_MODE_KEY for sub-register SR_AES_MODE in register AES_CTRL. More...
 
#define AES_NO_ERROR   (0)
 Constant AES_NO_ERROR for sub-register SR_AES_ER in register AES_STATUS. More...
 
#define AES_NOT_DONE   (0)
 Constant AES_NOT_DONE for sub-register SR_AES_DONE in register AES_STATUS. More...
 
#define AES_REQUEST   (1)
 Constant AES_REQUEST for sub-register SR_AES_REQUEST in register AES_CTRL. More...
 
#define ALTRATE_1_MBPS   (2)
 Constant ALTRATE_1_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define ALTRATE_250_KBPS   (0)
 Constant ALTRATE_250_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define ALTRATE_2_MBPS   (3)
 Constant ALTRATE_2_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define ALTRATE_500_KBPS   (1)
 Constant ALTRATE_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define ANT_CTRL_0   (0)
 Constant ANT_CTRL_0 for sub-register SR_ANT_CTRL in register ANT_DIV. More...
 
#define ANT_CTRL_1   (1)
 Constant ANT_CTRL_1 for sub-register SR_ANT_CTRL in register ANT_DIV. More...
 
#define ANT_CTRL_2   (2)
 Constant ANT_CTRL_2 for sub-register SR_ANT_CTRL in register ANT_DIV. More...
 
#define ANT_CTRL_3   (3)
 Constant ANT_CTRL_3 for sub-register SR_ANT_CTRL in register ANT_DIV. More...
 
#define ANT_DIV_DISABLE   (0)
 Constant ANT_DIV_DISABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV. More...
 
#define ANT_DIV_ENABLE   (1)
 Constant ANT_DIV_ENABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV. More...
 
#define ANT_EXT_SW_DISABLE   (0)
 Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV. More...
 
#define ANT_EXT_SW_ENABLE   (1)
 Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV. More...
 
#define ANT_SEL_ANTENNA_0   (0)
 Constant ANT_SEL_ANTENNA_0 for sub-register SR_ANT_SEL in register ANT_DIV. More...
 
#define ANT_SEL_ANTENNA_1   (1)
 Constant ANT_SEL_ANTENNA_1 for sub-register SR_ANT_SEL in register ANT_DIV. More...
 
#define BATMON_HR_HIGH   (1)
 Constant BATMON_HR_HIGH for sub-register SR_BATMON_HR in register BATMON. More...
 
#define BATMON_HR_LOW   (0)
 Constant BATMON_HR_LOW for sub-register SR_BATMON_HR in register BATMON. More...
 
#define BATMON_NOT_VALID   (0)
 Constant BATMON_NOT_VALID for sub-register SR_BATMON_OK in register BATMON. More...
 
#define BATMON_VALID   (1)
 Constant BATMON_VALID for sub-register SR_BATMON_OK in register BATMON. More...
 
#define CCA_CH_BUSY   (0)
 Constant CCA_CH_BUSY for sub-register SR_CCA_STATUS in register TRX_STATUS. More...
 
#define CCA_CH_IDLE   (1)
 Constant CCA_CH_IDLE for sub-register SR_CCA_STATUS in register TRX_STATUS. More...
 
#define CCA_COMPLETED   (1)
 Constant CCA_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS. More...
 
#define CCA_DETECTION_TIME_US   (135)
 
#define CCA_DURATION_SYM
 
#define CCA_MODE_0   (0)
 Constant CCA_MODE_0 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_MODE_1   (1)
 Constant CCA_MODE_1 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_MODE_2   (2)
 Constant CCA_MODE_2 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_MODE_3   (3)
 Constant CCA_MODE_3 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_NO_START   (0)
 Constant CCA_NO_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA. More...
 
#define CCA_ONGOING   (0)
 Constant CCA_ONGOING for sub-register SR_CCA_DONE in register TRX_STATUS. More...
 
#define CCA_PRE_START_DURATION_US   (20)
 
#define CCA_PREPARATION_DURATION_US   (50)
 
#define CCA_PROCESS_TIME_SYM   (1)
 
#define CCA_START   (1)
 Constant CCA_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA. More...
 
#define CLEAR_PD   (0)
 Constant CLEAR_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1. More...
 
#define CLKM_16MHZ   (5)
 Constant CLKM_16MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_1_16MHZ   (7)
 Constant CLKM_1_16MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_1_4MHZ   (6)
 Constant CLKM_1_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_1MHZ   (1)
 Constant CLKM_1MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_2MHZ   (2)
 Constant CLKM_2MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_4MHZ   (3)
 Constant CLKM_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_8MHZ   (4)
 Constant CLKM_8MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_NO_CLOCK   (0)
 Constant CLKM_NO_CLOCK for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More...
 
#define CLKM_SHA_DISABLE   (0)
 Constant CLKM_SHA_DISABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0. More...
 
#define CLKM_SHA_ENABLE   (1)
 Constant CLKM_SHA_ENABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0. More...
 
#define CRC16_NOT_VALID   (0)
 Constant CRC16_NOT_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI. More...
 
#define CRC16_VALID   (1)
 Constant CRC16_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI. More...
 
#define FLTR_RES_FT_DISABLE   (0)
 Constant FLTR_RES_FT_DISABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1. More...
 
#define FLTR_RES_FT_ENABLE   (1)
 Constant FLTR_RES_FT_ENABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1. More...
 
#define FRAME_VERSION_00   (0)
 Constant FRAME_VERSION_00 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define FRAME_VERSION_01   (1)
 Constant FRAME_VERSION_01 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define FRAME_VERSION_012   (2)
 Constant FRAME_VERSION_012 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define FRAME_VERSION_IGNORED   (3)
 Constant FRAME_VERSION_IGNORED for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define I_AM_COORD_DISABLE   (0)
 Constant I_AM_COORD_DISABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1. More...
 
#define I_AM_COORD_ENABLE   (1)
 Constant I_AM_COORD_ENABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1. More...
 
#define IRQ_HIGH_ACTIVE   (0)
 Constant IRQ_HIGH_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1. More...
 
#define IRQ_LOW_ACTIVE   (1)
 Constant IRQ_LOW_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1. More...
 
#define IRQ_MASK_MODE_OFF   (0)
 Constant IRQ_MASK_MODE_OFF for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1. More...
 
#define IRQ_MASK_MODE_ON   (1)
 Constant IRQ_MASK_MODE_ON for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1. More...
 
#define NORMAL   (0x0)
 Constant NORMAL for sub-register SR_TST_CTRL_DIG in register TST_CTRL_DIGI. More...
 
#define OQPSK_SCRAM_DISABLE   (0)
 Constant OQPSK_SCRAM_DISABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2. More...
 
#define OQPSK_SCRAM_ENABLE   (1)
 Constant OQPSK_SCRAM_ENABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2. More...
 
#define P_ON_TO_CLKM_AVAILABLE_MAX_US   (1000)
 
#define P_ON_TO_CLKM_AVAILABLE_TYP_US   (330)
 
#define P_ON_TO_TRX_OFF_AFTER_CLKM_AVAILABLE_MAX_US   (1000)
 
#define P_ON_TO_TRX_OFF_AFTER_CLKM_AVAILABLE_TYP_US   (360)
 
#define PA_EXT_DISABLE   (0)
 Constants. More...
 
#define PA_EXT_ENABLE   (1)
 Constant PA_EXT_enable for sub-register SR_PA_EXT_EN. More...
 
#define PART_NUM_AT86RF233   (0x0B)
 Constant PART_NUM_AT86RF233 for sub-register SR_PART_NUM in register PART_NUM. More...
 
#define PLL_LOCK_DURATION_MAX_US   (250)
 
#define PRE_TX_DURATION_US   (32)
 
#define PROM_MODE_DISABLE   (0)
 Constant PROM_MODE_DISABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1. More...
 
#define PROM_MODE_ENABLE   (1)
 Constant PROM_MODE_ENABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1. More...
 
#define REG_BASE_ADDR   (0x00)
 Register addresses. More...
 
#define RG_AES_CTRL   (0x03)
 Offset for register AES_CTRL. More...
 
#define RG_AES_CTRL_MIRROR   (0x14)
 Offset for register AES_CTRL_MIRROR. More...
 
#define RG_AES_STATE_KEY_0   (0x04)
 Offset for register AES_STATE_KEY_0. More...
 
#define RG_AES_STATUS   (0x02)
 Offset for register AES_STATUS. More...
 
#define RG_ANT_DIV   (0x0D)
 Offset for register ANT_DIV. More...
 
#define RG_BATMON   (0x11)
 Offset for register BATMON. More...
 
#define RG_CC_CTRL_0   (0x13)
 Offset for register CC_CTRL_0. More...
 
#define RG_CC_CTRL_1   (0x14)
 Offset for register CC_CTRL_1. More...
 
#define RG_CCA_THRES   (0x09)
 Offset for register CCA_THRES. More...
 
#define RG_CSMA_BE   (0x2F)
 Offset for register CSMA_BE. More...
 
#define RG_CSMA_SEED_0   (0x2D)
 Offset for register CSMA_SEED_0. More...
 
#define RG_CSMA_SEED_1   (0x2E)
 Offset for register CSMA_SEED_1. More...
 
#define RG_ED   (0x01)
 Offset for register ED. More...
 
#define RG_FTN_CTRL   (0x18)
 Offset for register FTN_CTRL. More...
 
#define RG_IEEE_ADDR_0   (0x24)
 Offset for register IEEE_ADDR_0. More...
 
#define RG_IEEE_ADDR_1   (0x25)
 Offset for register IEEE_ADDR_1. More...
 
#define RG_IEEE_ADDR_2   (0x26)
 Offset for register IEEE_ADDR_2. More...
 
#define RG_IEEE_ADDR_3   (0x27)
 Offset for register IEEE_ADDR_3. More...
 
#define RG_IEEE_ADDR_4   (0x28)
 Offset for register IEEE_ADDR_4. More...
 
#define RG_IEEE_ADDR_5   (0x29)
 Offset for register IEEE_ADDR_5. More...
 
#define RG_IEEE_ADDR_6   (0x2A)
 Offset for register IEEE_ADDR_6. More...
 
#define RG_IEEE_ADDR_7   (0x2B)
 Offset for register IEEE_ADDR_7. More...
 
#define RG_IRQ_MASK   (0x0E)
 Offset for register IRQ_MASK. More...
 
#define RG_IRQ_STATUS   (0x0F)
 Offset for register IRQ_STATUS. More...
 
#define RG_LQI   (0x00)
 Offset for register LQI. More...
 
#define RG_MAN_ID_0   (0x1E)
 Offset for register MAN_ID_0. More...
 
#define RG_MAN_ID_1   (0x1F)
 Offset for register MAN_ID_1. More...
 
#define RG_PAN_ID_0   (0x22)
 Offset for register PAN_ID_0. More...
 
#define RG_PAN_ID_1   (0x23)
 Offset for register PAN_ID_1. More...
 
#define RG_PART_NUM   (0x1C)
 Offset for register PART_NUM. More...
 
#define RG_PHY_CC_CCA   (0x08)
 Offset for register PHY_CC_CCA. More...
 
#define RG_PHY_ED_LEVEL   (0x07)
 Offset for register PHY_ED_LEVEL. More...
 
#define RG_PHY_PMU_VALUE   (0x3B)
 Offset for register PHY_PMU_VALUE. More...
 
#define RG_PHY_RSSI   (0x06)
 Offset for register PHY_RSSI. More...
 
#define RG_PHY_TX_PWR   (0x05)
 Offset for register PHY_TX_PWR. More...
 
#define RG_PLL_CF   (0x1A)
 Offset for register PLL_CF. More...
 
#define RG_PLL_DCU   (0x1B)
 Offset for register PLL_DCU. More...
 
#define RG_RX_CTRL   (0x0A)
 Offset for register RX_CTRL. More...
 
#define RG_RX_STATUS   (0x02)
 Offset for register RX_STATUS. More...
 
#define RG_RX_SYN   (0x15)
 Offset for register RX_SYN. More...
 
#define RG_SFD_VALUE   (0x0B)
 Offset for register SFD_VALUE. More...
 
#define RG_SHORT_ADDR_0   (0x20)
 Offset for register SHORT_ADDR_0. More...
 
#define RG_SHORT_ADDR_1   (0x21)
 Offset for register SHORT_ADDR_1. More...
 
#define RG_TRX_CTRL_0   (0x03)
 Offset for register TRX_CTRL_0. More...
 
#define RG_TRX_CTRL_1   (0x04)
 Offset for register TRX_CTRL_1. More...
 
#define RG_TRX_CTRL_2   (0x0C)
 Offset for register TRX_CTRL_2. More...
 
#define RG_TRX_PAGE   (0x00)
 Offset for register TRX_PAGE. More...
 
#define RG_TRX_RPC   (0x16)
 Offset for register TRX_RPC. More...
 
#define RG_TRX_STATE   (0x02)
 Offset for register TRX_STATE. More...
 
#define RG_TRX_STATUS   (0x01)
 Offset for register TRX_STATUS. More...
 
#define RG_TST_CTRL_DIGI   (0x36)
 Offset for register TST_CTRL_DIGI. More...
 
#define RG_VERSION_NUM   (0x1D)
 Offset for register VERSION_NUM. More...
 
#define RG_VREG_CTRL   (0x10)
 Offset for register VREG_CTRL. More...
 
#define RG_XAH_CTRL_0   (0x2C)
 Offset for register XAH_CTRL_0. More...
 
#define RG_XAH_CTRL_1   (0x17)
 Offset for register XAH_CTRL_1. More...
 
#define RG_XAH_CTRL_2   (0x19)
 Offset for register XAH_CTRL_2. More...
 
#define RG_XOSC_CTRL   (0x12)
 Offset for register XOSC_CTRL. More...
 
#define RSSI_BASE_VAL_DBM   (-91)
 
#define RST_PULSE_WIDTH_NS   (625)
 Typical timing values. More...
 
#define RST_PULSE_WIDTH_US   (10) /* ((RST_PULSE_WIDTH_NS + 999) / 1000) */
 
#define RX_BL_CTRL_DISABLE   (0)
 Constant RX_BL_CTRL_DISABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1. More...
 
#define RX_BL_CTRL_ENABLE   (1)
 Constant RX_BL_CTRL_ENABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1. More...
 
#define RX_DISABLE   (1)
 Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More...
 
#define RX_ENABLE   (0)
 Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More...
 
#define RX_OFFSET_16US   (3)
 Constant RX_OFFSET_16US for sub-register SR_RX_RPC_CTRL in register TRX_RPC. More...
 
#define RX_OFFSET_MIN   (0)
 Constant RX_OFFSET_MIN for sub-register SR_RX_RPC_CTRL in register TRX_RPC. More...
 
#define RX_SAFE_MODE_DISABLE   (0)
 Constant RX_SAFE_MODE_DISABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2. More...
 
#define RX_SAFE_MODE_ENABLE   (1)
 Constant RX_SAFE_MODE_ENABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2. More...
 
#define RX_TIMESTAMPING_DISABLE   (0)
 Constant RX_TIMESTAMPING_DISABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1. More...
 
#define RX_TIMESTAMPING_ENABLE   (1)
 Constant RX_TIMESTAMPING_ENABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1. More...
 
#define RXAPPENDIX_BASE_ADDR   (0x00)
 Base address and size for RX frame appendix. More...
 
#define RXAPPENDIX_SIZE   (3)
 
#define SET_PD   (1)
 Constant SET_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1. More...
 
#define SLEEP_TO_TRX_OFF_MAX_US   (1000)
 
#define SLEEP_TO_TRX_OFF_TYP_US   (210)
 
#define SPI_CMD_MODE_DEFAULT   (0)
 Constant SPI_CMD_MODE_DEFAULT for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More...
 
#define SPI_CMD_MODE_IRQ_STATUS   (3)
 Constant SPI_CMD_MODE_IRQ_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More...
 
#define SPI_CMD_MODE_PHY_RSSI   (2)
 Constant SPI_CMD_MODE_PHY_RSSI for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More...
 
#define SPI_CMD_MODE_TRX_STATUS   (1)
 Constant SPI_CMD_MODE_TRX_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More...
 
#define SR_AACK_ACK_TIME   0x17, 0x04, 2
 Sub-register access. More...
 
#define SR_AACK_DIS_ACK   0x2E, 0x10, 4
 Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_FLTR_RES_FT   0x17, 0x20, 5
 Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1. More...
 
#define SR_AACK_FVN_MODE   0x2E, 0xC0, 6
 Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_I_AM_COORD   0x2E, 0x08, 3
 Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_PROM_MODE   0x17, 0x02, 1
 Access parameters for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1. More...
 
#define SR_AACK_SET_PD   0x2E, 0x20, 5
 Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_SPC_EN   0x17, 0x01, 0
 Access parameters for sub-register AACK_SPC_EN in register RG_XAH_CTRL_1. More...
 
#define SR_AACK_UPLD_RES_FT   0x17, 0x10, 4
 Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1. More...
 
#define SR_AES_DIR   0x03, 0x08, 3
 Access parameters for sub-register AES_DIR in register RG_AES_CTRL. More...
 
#define SR_AES_DONE   0x02, 0x01, 0
 Access parameters for sub-register AES_DONE in register RG_AES_STATUS. More...
 
#define SR_AES_ER   0x02, 0x80, 7
 Access parameters for sub-register AES_ER in register RG_AES_STATUS. More...
 
#define SR_AES_MODE   0x03, 0x70, 4
 Access parameters for sub-register AES_MODE in register RG_AES_CTRL. More...
 
#define SR_AES_REQUEST   0x03, 0x80, 7
 Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL. More...
 
#define SR_ANT_CTRL   0x0D, 0x03, 0
 Access parameters for sub-register ANT_CTRL in register RG_ANT_DIV. More...
 
#define SR_ANT_DIV_EN   0x0D, 0x08, 3
 Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV. More...
 
#define SR_ANT_EXT_SW_EN   0x0D, 0x04, 2
 Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV. More...
 
#define SR_ANT_SEL   0x0D, 0x80, 7
 Access parameters for sub-register ANT_SEL in register RG_ANT_DIV. More...
 
#define SR_ARET_CSMA_RETRIES   0x19, 0x0E, 1
 Access parameters for sub-register ARET_CSMA_RETRIES in register RG_XAH_CTRL_2. More...
 
#define SR_ARET_FRAME_RETRIES   0x19, 0xF0, 4
 Access parameters for sub-register ARET_FRAME_RETRIES in register RG_XAH_CTRL_2. More...
 
#define SR_ARET_TX_TS_EN   0x17, 0x80, 7
 Access parameters for sub-register ARET_TX_TS_EN in register RG_XAH_CTRL_1. More...
 
#define SR_AVDD_OK   0x10, 0x40, 6
 Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL. More...
 
#define SR_AVREG_EXT   0x10, 0x80, 7
 Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL. More...
 
#define SR_BATMON_HR   0x11, 0x10, 4
 Access parameters for sub-register BATMON_HR in register RG_BATMON. More...
 
#define SR_BATMON_OK   0x11, 0x20, 5
 Access parameters for sub-register BATMON_OK in register RG_BATMON. More...
 
#define SR_BATMON_VTH   0x11, 0x0F, 0
 Access parameters for sub-register BATMON_VTH in register RG_BATMON. More...
 
#define SR_CC_BAND   0x14, 0x0F, 0
 Access parameters for sub-register CC_BAND in register RG_CC_CTRL_1. More...
 
#define SR_CC_NUMBER   0x13, 0xFF, 0
 Access parameters for sub-register CC_NUMBER in register RG_CC_CTRL_0. More...
 
#define SR_CCA_DONE   0x01, 0x80, 7
 Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS. More...
 
#define SR_CCA_ED_THRES   0x09, 0x0F, 0
 Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES. More...
 
#define SR_CCA_MODE   0x08, 0x60, 5
 Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA. More...
 
#define SR_CCA_REQUEST   0x08, 0x80, 7
 Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA. More...
 
#define SR_CCA_STATUS   0x01, 0x40, 6
 Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS. More...
 
#define SR_CHANNEL   0x08, 0x1F, 0
 Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA. More...
 
#define SR_CLKM_CTRL   0x03, 0x07, 0
 Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0. More...
 
#define SR_CLKM_SHA_SEL   0x03, 0x08, 3
 Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0. More...
 
#define SR_CSMA_SEED_0   0x2D, 0xFF, 0
 Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0. More...
 
#define SR_CSMA_SEED_1   0x2E, 0x07, 0
 Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1. More...
 
#define SR_DVDD_OK   0x10, 0x04, 2
 Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL. More...
 
#define SR_DVREG_EXT   0x10, 0x08, 3
 Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL. More...
 
#define SR_ED_APX   0x01, 0xFF, 0
 Access parameters for sub-register ED_APX in register RG_ED. More...
 
#define SR_ED_LEVEL   0x07, 0xFF, 0
 Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL. More...
 
#define SR_FTN_START   0x18, 0x80, 7
 Access parameters for sub-register FTN_START in register RG_FTN_CTRL. More...
 
#define SR_IEEE_ADDR_0   0x24, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0. More...
 
#define SR_IEEE_ADDR_1   0x25, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1. More...
 
#define SR_IEEE_ADDR_2   0x26, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2. More...
 
#define SR_IEEE_ADDR_3   0x27, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3. More...
 
#define SR_IEEE_ADDR_4   0x28, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4. More...
 
#define SR_IEEE_ADDR_5   0x29, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5. More...
 
#define SR_IEEE_ADDR_6   0x2A, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6. More...
 
#define SR_IEEE_ADDR_7   0x2B, 0xFF, 0
 Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7. More...
 
#define SR_IPAN_RPC_EN   0x16, 0x02, 1
 Access parameters for sub-register IPAN_RPC_EN in register RG_TRX_RPC. More...
 
#define SR_IRQ_0_PLL_LOCK   0x0F, 0x01, 0
 Access parameters for sub-register IRQ_0_PLL_LOCK in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_1_PLL_UNLOCK   0x0F, 0x02, 1
 Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_2_EXT_EN   0x04, 0x40, 6
 Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1. More...
 
#define SR_IRQ_2_RX_START   0x0F, 0x04, 2
 Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_3_TRX_END   0x0F, 0x08, 3
 Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_4_CCA_ED_DONE   0x0F, 0x10, 4
 Access parameters for sub-register IRQ_4_CCA_ED_DONE in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_5_AMI   0x0F, 0x20, 5
 Access parameters for sub-register IRQ_5_AMI in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_6_TRX_UR   0x0F, 0x40, 6
 Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_7_BAT_LOW   0x0F, 0x80, 7
 Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS. More...
 
#define SR_IRQ_MASK   0x0E, 0xFF, 0
 Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK. More...
 
#define SR_IRQ_MASK_MODE   0x04, 0x02, 1
 Access parameters for sub-register IRQ_MASK_MODE in register RG_TRX_CTRL_1. More...
 
#define SR_IRQ_POLARITY   0x04, 0x01, 0
 Access parameters for sub-register IRQ_POLARITY in register RG_TRX_CTRL_1. More...
 
#define SR_LQI_APX   0x00, 0xFF, 0
 Access parameters for sub-register LQI_APX in register RG_LQI. More...
 
#define SR_MAN_ID_0   0x1E, 0xFF, 0
 Access parameters for sub-register MAN_ID_0 in register RG_MAN_ID_0. More...
 
#define SR_MAN_ID_1   0x1F, 0xFF, 0
 Access parameters for sub-register MAN_ID_1 in register RG_MAN_ID_1. More...
 
#define SR_MAX_BE   0x2F, 0xF0, 4
 Access parameters for sub-register MAX_BE in register RG_CSMA_BE. More...
 
#define SR_MAX_CSMA_RETRIES   0x2C, 0x0E, 1
 Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0. More...
 
#define SR_MAX_FRAME_RETRIES   0x2C, 0xF0, 4
 Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0. More...
 
#define SR_MIN_BE   0x2F, 0x0F, 0
 Access parameters for sub-register MIN_BE in register RG_CSMA_BE. More...
 
#define SR_OQPSK_DATA_RATE   0x0C, 0x07, 0
 Access parameters for sub-register OQPSK_DATA_RATE in register RG_TRX_CTRL_2. More...
 
#define SR_OQPSK_SCRAM_EN   0x0C, 0x20, 5
 Access parameters for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2. More...
 
#define SR_PA_EXT_EN   0x04, 0x80, 7
 Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1. More...
 
#define SR_PAN_ID_0   0x22, 0xFF, 0
 Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0. More...
 
#define SR_PAN_ID_1   0x23, 0xFF, 0
 Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1. More...
 
#define SR_PART_NUM   0x1C, 0xFF, 0
 Access parameters for sub-register PART_NUM in register RG_PART_NUM. More...
 
#define SR_PDT_RPC_EN   0x16, 0x10, 4
 Access parameters for sub-register PDT_RPC_EN in register RG_TRX_RPC. More...
 
#define SR_PDT_THRES   0x0A, 0x0F, 0
 Access parameters for sub-register PDT_THRES in register RG_RX_CTRL. More...
 
#define SR_PLL_CF   0x1A, 0x0F, 0
 Access parameters for sub-register PLL_CF in register RG_PLL_CF. More...
 
#define SR_PLL_CF_START   0x1A, 0x80, 7
 Access parameters for sub-register PLL_CF_START in register RG_PLL_CF. More...
 
#define SR_PLL_DCU_START   0x1B, 0x80, 7
 Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU. More...
 
#define SR_PLL_RPC_EN   0x16, 0x08, 3
 Access parameters for sub-register PLL_RPC_EN in register RG_TRX_RPC. More...
 
#define SR_PMU_VALUE   0x3B, 0xFF, 0
 Access parameters for sub-register PMU_VALUE in register RG_PHY_PMU_VALUE. More...
 
#define SR_RND_VALUE   0x06, 0x60, 5
 Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI. More...
 
#define SR_RSSI   0x06, 0x1F, 0
 Access parameters for sub-register RSSI in register RG_PHY_RSSI. More...
 
#define SR_RX_BL_CTRL   0x04, 0x10, 4
 Access parameters for sub-register RX_BL_CTRL in register RG_TRX_CTRL_1. More...
 
#define SR_RX_CRC_VALID   0x06, 0x80, 7
 Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI. More...
 
#define SR_RX_CRC_VALID_APX   0x02, 0x80, 7
 Access parameters for sub-register RX_CRC_VALID_APX in register RG_RX_STATUS. More...
 
#define SR_RX_PDT_DIS   0x15, 0x80, 7
 Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN. More...
 
#define SR_RX_PDT_LEVEL   0x15, 0x0F, 0
 Access parameters for sub-register RX_PDT_LEVEL in register RG_RX_SYN. More...
 
#define SR_RX_RPC_CTRL   0x16, 0xC0, 6
 Access parameters for sub-register RX_RPC_CTRL in register RG_TRX_RPC. More...
 
#define SR_RX_RPC_EN   0x16, 0x20, 5
 Access parameters for sub-register RX_RPC_EN in register RG_TRX_RPC. More...
 
#define SR_RX_SAFE_MODE   0x0C, 0x80, 7
 Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2. More...
 
#define SR_SFD_VALUE   0x0B, 0xFF, 0
 Access parameters for sub-register SFD_VALUE in register RG_SFD_VALUE. More...
 
#define SR_SHORT_ADDR_0   0x20, 0xFF, 0
 Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0. More...
 
#define SR_SHORT_ADDR_1   0x21, 0xFF, 0
 Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1. More...
 
#define SR_SLOTTED_OPERATION   0x2C, 0x01, 0
 Access parameters for sub-register SLOTTED_OPERATION in register RG_XAH_CTRL_0. More...
 
#define SR_SPI_CMD_MODE   0x04, 0x0C, 2
 Access parameters for sub-register SPI_CMD_MODE in register RG_TRX_CTRL_1. More...
 
#define SR_TRAC_STATUS   0x02, 0xE0, 5
 Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE. More...
 
#define SR_TRAC_STATUS_APX   0x02, 0x70, 4
 Access parameters for sub-register TRAC_STATUS_APX in register RG_RX_STATUS. More...
 
#define SR_TRX_CMD   0x02, 0x1F, 0
 Access parameters for sub-register TRX_CMD in register RG_TRX_STATE. More...
 
#define SR_TRX_STATUS   0x01, 0x1F, 0
 Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS. More...
 
#define SR_TST_CTRL_DIG   0x36, 0x0F, 0
 Access parameters for sub-register TST_CTRL_DIG in register RG_TST_CTRL_DIGI. More...
 
#define SR_TX_AUTO_CRC_ON   0x04, 0x20, 5
 Access parameters for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1. More...
 
#define SR_TX_PWR   0x05, 0x0F, 0
 Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR. More...
 
#define SR_VERSION_NUM   0x1D, 0xFF, 0
 Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM. More...
 
#define SR_XAH_TX_RPC_EN   0x16, 0x04, 2
 Access parameters for sub-register XAH_TX_RPC_EN in register RG_TRX_RPC. More...
 
#define SR_XTAL_MODE   0x12, 0xF0, 4
 Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL. More...
 
#define SR_XTAL_TRIM   0x12, 0x0F, 0
 Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL. More...
 
#define T_OCT_US   (32)
 
#define T_SYM_US   (16)
 
#define THRES_ANT_DIV_DISABLE   (0x7)
 Constant THRES_ANT_DIV_DISABLE for sub-register SR_PDT_THRES in register RX_CTRL. More...
 
#define THRES_ANT_DIV_ENABLE   (0x3)
 Constant THRES_ANT_DIV_ENABLE for sub-register SR_PDT_THRES in register RX_CTRL. More...
 
#define TRANSCEIVER_NAME   "AT86RF233"
 
#define TRX_IRQ_DELAY_US   (9)
 
#define TRX_OFF_TO_PLL_ON_TIME_US   (80)
 
#define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES   (35)
 
#define TRX_SUPPORTED_CHANNELS   (0x07FFF800)
 Parameter definitions. More...
 
#define TST_CONT_TX   (0xF)
 Constant TST_CONT_TX for sub-register SR_TST_CTRL_DIG in register TST_CTRL_DIGI. More...
 
#define TX_ARET_TIMESTAMPING_DISABLE   (0)
 Constant TX_ARET_TIMESTAMPING_DISABLE for sub-register SR_ARET_TX_TS_EN in register XAH_CTRL_1. More...
 
#define TX_ARET_TIMESTAMPING_ENABLE   (1)
 Constant TX_ARET_TIMESTAMPING_ENABLE for sub-register SR_ARET_TX_TS_EN in register XAH_CTRL_1. More...
 
#define TX_AUTO_CRC_DISABLE   (0)
 Constant TX_AUTO_CRC_DISABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1. More...
 
#define TX_AUTO_CRC_ENABLE   (1)
 Constant TX_AUTO_CRC_ENABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1. More...
 
#define TX_PWR_TOLERANCE   (0x80)
 
#define UPLD_RES_FT_DISABLE   (0)
 Constant UPLD_RES_FT_DISABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1. More...
 
#define UPLD_RES_FT_ENABLE   (1)
 Constant UPLD_RES_FT_ENABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1. More...
 
#define VERSION_NUM_AT86RF233   (0x01)
 Constant VERSION_NUM_AT86RF233 for sub-register SR_VERSION_NUM in register VERSION_NUM. More...
 

Typedefs

typedef enum tal_trx_status_tag tal_trx_status_t
 sub-register TRX_STATUS in register TRX_STATUS More...
 
typedef enum trx_cmd_tag trx_cmd_t
 Enumerations. More...
 
typedef enum trx_irq_reason_tag trx_irq_reason_t
 sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS More...
 
typedef enum trx_trac_status_tag trx_trac_status_t
 sub-register TRAC_STATUS in register TRX_STATE More...
 

Enumerations

enum  tal_trx_status_tag {
  P_ON = (0),
  BUSY_RX = (1),
  BUSY_TX = (2),
  RX_ON = (6),
  TRX_OFF = (8),
  PLL_ON = (9),
  TRX_SLEEP = (15),
  BUSY_RX_AACK = (17),
  BUSY_TX_ARET = (18),
  RX_AACK_ON = (22),
  TX_ARET_ON = (25),
  RX_ON_NOCLK = (28),
  RX_AACK_ON_NOCLK = (29),
  BUSY_RX_AACK_NOCLK = (30),
  STATE_TRANSITION_IN_PROGRESS = (31),
  P_ON = (0x00),
  BUSY_RX = (0x01),
  BUSY_TX = (0x02),
  RX_ON = (0x06),
  TRX_OFF = (0x08),
  PLL_ON = (0x09),
  TRX_SLEEP = (0x0F),
  BUSY_RX_AACK = (0x11),
  BUSY_TX_ARET = (0x12),
  RX_AACK_ON = (0x16),
  TX_ARET_ON = (0x19),
  RX_ON_NOCLK = (0x1C),
  RX_AACK_ON_NOCLK = (0x1D),
  BUSY_RX_AACK_NOCLK = (0x1E),
  STATE_TRANSITION_IN_PROGRESS = (0x1F),
  P_ON = (0x00),
  BUSY_RX = (0x01),
  BUSY_TX = (0x02),
  RX_ON = (0x06),
  TRX_OFF = (0x08),
  PLL_ON = (0x09),
  TRX_SLEEP = (0x0F),
  BUSY_RX_AACK = (0x11),
  BUSY_TX_ARET = (0x12),
  RX_AACK_ON = (0x16),
  TX_ARET_ON = (0x19),
  RX_ON_NOCLK = (0x1C),
  RX_AACK_ON_NOCLK = (0x1D),
  BUSY_RX_AACK_NOCLK = (0x1E),
  STATE_TRANSITION_IN_PROGRESS = (0x1F),
  P_ON = (0x00),
  BUSY_RX = (0x01),
  BUSY_TX = (0x02),
  RX_ON = (0x06),
  TRX_OFF = (0x08),
  PLL_ON = (0x09),
  TRX_SLEEP = (0x0F),
  PREP_DEEP_SLEEP = (0x10),
  BUSY_RX_AACK = (0x11),
  BUSY_TX_ARET = (0x12),
  RX_AACK_ON = (0x16),
  TX_ARET_ON = (0x19),
  STATE_TRANSITION_IN_PROGRESS = (0x1F),
  TRX_DEEP_SLEEP = (0x20),
  P_ON = (0x00),
  BUSY_RX = (0x01),
  BUSY_TX = (0x02),
  RX_ON = (0x06),
  TRX_OFF = (0x08),
  PLL_ON = (0x09),
  TRX_SLEEP = (0x0F),
  BUSY_RX_AACK = (0x11),
  BUSY_TX_ARET = (0x12),
  RX_AACK_ON = (0x16),
  TX_ARET_ON = (0x19),
  STATE_TRANSITION_IN_PROGRESS = (0x1F)
}
 sub-register TRX_STATUS in register TRX_STATUS More...
 
enum  trx_cmd_tag {
  CMD_NOP = (0),
  CMD_TX_START = (2),
  CMD_FORCE_TRX_OFF = (3),
  CMD_FORCE_PLL_ON = (4),
  CMD_RX_ON = (6),
  CMD_TRX_OFF = (8),
  CMD_PLL_ON = (9),
  CMD_SLEEP = (15),
  CMD_RX_AACK_ON = (22),
  CMD_TX_ARET_ON = (25),
  CMD_NOP = (0x00),
  CMD_TX_START = (0x02),
  CMD_FORCE_TRX_OFF = (0x03),
  CMD_FORCE_PLL_ON = (0x04),
  CMD_RX_ON = (0x06),
  CMD_TRX_OFF = (0x08),
  CMD_PLL_ON = (0x09),
  CMD_RX_AACK_ON = (0x16),
  CMD_TX_ARET_ON = (0x19),
  CMD_SLEEP = (0x0F),
  CMD_NOP = (0x00),
  CMD_TX_START = (0x02),
  CMD_FORCE_TRX_OFF = (0x03),
  CMD_FORCE_PLL_ON = (0x04),
  CMD_RX_ON = (0x06),
  CMD_TRX_OFF = (0x08),
  CMD_PLL_ON = (0x09),
  CMD_RX_AACK_ON = (0x16),
  CMD_TX_ARET_ON = (0x19),
  CMD_SLEEP = (0x0F),
  CMD_NOP = (0x00),
  CMD_TX_START = (0x02),
  CMD_FORCE_TRX_OFF = (0x03),
  CMD_FORCE_PLL_ON = (0x04),
  CMD_RX_ON = (0x06),
  CMD_TRX_OFF = (0x08),
  CMD_PLL_ON = (0x09),
  CMD_PREP_DEEP_SLEEP = (0x10),
  CMD_RX_AACK_ON = (0x16),
  CMD_TX_ARET_ON = (0x19),
  CMD_SLEEP = (0x0F),
  CMD_DEEP_SLEEP = (0x20),
  CMD_NOP = (0x00),
  CMD_TX_START = (0x02),
  CMD_FORCE_TRX_OFF = (0x03),
  CMD_FORCE_PLL_ON = (0x04),
  CMD_RX_ON = (0x06),
  CMD_TRX_OFF = (0x08),
  CMD_PLL_ON = (0x09),
  CMD_RX_AACK_ON = (0x16),
  CMD_TX_ARET_ON = (0x19),
  CMD_SLEEP = (0x0F)
}
 Enumerations. More...
 
enum  trx_irq_reason_tag {
  TRX_NO_IRQ = (0x00),
  TRX_IRQ_PLL_LOCK = (0x01),
  TRX_IRQ_PLL_UNLOCK = (0x02),
  TRX_IRQ_RX_START = (0x04),
  TRX_IRQ_TRX_END = (0x08),
  TRX_IRQ_CCA_ED_READY = (0x10),
  TRX_IRQ_AMI = (0x20),
  TRX_IRQ_TRX_UR = (0x40),
  TRX_IRQ_BAT_LOW = (0x80),
  TRX_IRQ_7_BAT_LOW = (0x80),
  TRX_IRQ_6_TRX_UR = (0x40),
  TRX_IRQ_5_AMI = (0x20),
  TRX_IRQ_4_CCA_ED_DONE = (0x10),
  TRX_IRQ_3_TRX_END = (0x08),
  TRX_IRQ_2_RX_START = (0x04),
  TRX_IRQ_1_PLL_UNLOCK = (0x02),
  TRX_IRQ_0_PLL_LOCK = (0x01),
  TRX_NO_IRQ = (0x00),
  TRX_IRQ_7_BAT_LOW = (0x80),
  TRX_IRQ_6_TRX_UR = (0x40),
  TRX_IRQ_5_AMI = (0x20),
  TRX_IRQ_4_CCA_ED_DONE = (0x10),
  TRX_IRQ_3_TRX_END = (0x08),
  TRX_IRQ_2_RX_START = (0x04),
  TRX_IRQ_1_PLL_UNLOCK = (0x02),
  TRX_IRQ_0_PLL_LOCK = (0x01),
  TRX_NO_IRQ = (0x00),
  TRX_IRQ_7_BAT_LOW = (0x80),
  TRX_IRQ_6_TRX_UR = (0x40),
  TRX_IRQ_5_AMI = (0x20),
  TRX_IRQ_4_CCA_ED_DONE = (0x10),
  TRX_IRQ_3_TRX_END = (0x08),
  TRX_IRQ_2_RX_START = (0x04),
  TRX_IRQ_1_PLL_UNLOCK = (0x02),
  TRX_IRQ_0_PLL_LOCK = (0x01),
  TRX_NO_IRQ = (0x00),
  TRX_IRQ_7_BAT_LOW = (0x80),
  TRX_IRQ_6_TRX_UR = (0x40),
  TRX_IRQ_5_AMI = (0x20),
  TRX_IRQ_4_CCA_ED_DONE = (0x10),
  TRX_IRQ_3_TRX_END = (0x08),
  TRX_IRQ_2_RX_START = (0x04),
  TRX_IRQ_1_PLL_UNLOCK = (0x02),
  TRX_IRQ_0_PLL_LOCK = (0x01),
  TRX_NO_IRQ = (0x00)
}
 sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS More...
 
enum  trx_trac_status_tag {
  TRAC_SUCCESS = 0,
  TRAC_SUCCESS_DATA_PENDING = 1,
  TRAC_WAIT_FOR_ACK = 2,
  TRAC_CHANNEL_ACCESS_FAILURE = 3,
  TRAC_NO_ACK = 5,
  TRAC_INVALID = 7,
  TRAC_SUCCESS = (0),
  TRAC_SUCCESS_DATA_PENDING = (1),
  TRAC_SUCCESS_WAIT_FOR_ACK = (2),
  TRAC_CHANNEL_ACCESS_FAILURE = (3),
  TRAC_NO_ACK = (5),
  TRAC_INVALID = (7),
  TRAC_SUCCESS = (0x00),
  TRAC_SUCCESS_DATA_PENDING = (0x01),
  TRAC_SUCCESS_WAIT_FOR_ACK = (0x02),
  TRAC_CHANNEL_ACCESS_FAILURE = (0x03),
  TRAC_NO_ACK = (0x05),
  TRAC_INVALID = (0x07),
  TRAC_SUCCESS = (0),
  TRAC_SUCCESS_DATA_PENDING = (1),
  TRAC_SUCCESS_WAIT_FOR_ACK = (2),
  TRAC_CHANNEL_ACCESS_FAILURE = (3),
  TRAC_NO_ACK = (5),
  TRAC_INVALID = (7),
  TRAC_SUCCESS = (0),
  TRAC_SUCCESS_DATA_PENDING = (1),
  TRAC_SUCCESS_WAIT_FOR_ACK = (2),
  TRAC_CHANNEL_ACCESS_FAILURE = (3),
  TRAC_NO_ACK = (5),
  TRAC_INVALID = (7)
}
 sub-register TRAC_STATUS in register TRX_STATE More...
 

#define AACK_SPC_DISABLE   (0)

Constant AACK_SPC_DISABLE for sub-register SR_AACK_SPC_EN in register XAH_CTRL_1.

#define AACK_SPC_ENABLE   (1)

Constant AACK_SPC_ENABLE for sub-register SR_AACK_SPC_EN in register XAH_CTRL_1.

#define ACK_DISABLE   (1)

Constant ACK_DISABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1.

#define ACK_ENABLE   (0)

Constant ACK_ENABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1.

#define ACK_TIME_12_SYMBOLS   (0)

Constant ACK_TIME_12_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1.

#define ACK_TIME_2_SYMBOLS   (1)

Constant ACK_TIME_2_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1.

#define AES_BASE_ADDR   (0x80)

Base address for Transceiver AES address space.

#define AES_DIR_DECRYPT   (1)

Constant AES_DIR_DECRYPT for sub-register SR_AES_DIR in register AES_CTRL.

#define AES_DIR_ENCRYPT   (0)

Constant AES_DIR_ENCRYPT for sub-register SR_AES_DIR in register AES_CTRL.

#define AES_DONE   (1)

Constant AES_DONE for sub-register SR_AES_DONE in register AES_STATUS.

#define AES_ERROR   (1)

Constant AES_ERROR for sub-register SR_AES_ER in register AES_STATUS.

#define AES_MODE_CBC   (2)

Constant AES_MODE_CBC for sub-register SR_AES_MODE in register AES_CTRL.

#define AES_MODE_ECB   (0)

Constant AES_MODE_ECB for sub-register SR_AES_MODE in register AES_CTRL.

#define AES_MODE_KEY   (1)

Constant AES_MODE_KEY for sub-register SR_AES_MODE in register AES_CTRL.

#define AES_NO_ERROR   (0)

Constant AES_NO_ERROR for sub-register SR_AES_ER in register AES_STATUS.

#define AES_NOT_DONE   (0)

Constant AES_NOT_DONE for sub-register SR_AES_DONE in register AES_STATUS.

#define AES_REQUEST   (1)

Constant AES_REQUEST for sub-register SR_AES_REQUEST in register AES_CTRL.

#define ALTRATE_1_MBPS   (2)

Constant ALTRATE_1_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define ALTRATE_250_KBPS   (0)

Constant ALTRATE_250_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define ALTRATE_2_MBPS   (3)

Constant ALTRATE_2_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define ALTRATE_500_KBPS   (1)

Constant ALTRATE_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define ANT_CTRL_0   (0)

Constant ANT_CTRL_0 for sub-register SR_ANT_CTRL in register ANT_DIV.

#define ANT_CTRL_1   (1)

Constant ANT_CTRL_1 for sub-register SR_ANT_CTRL in register ANT_DIV.

#define ANT_CTRL_2   (2)

Constant ANT_CTRL_2 for sub-register SR_ANT_CTRL in register ANT_DIV.

#define ANT_CTRL_3   (3)

Constant ANT_CTRL_3 for sub-register SR_ANT_CTRL in register ANT_DIV.

#define ANT_DIV_DISABLE   (0)

Constant ANT_DIV_DISABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV.

#define ANT_DIV_ENABLE   (1)

Constant ANT_DIV_ENABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV.

#define ANT_EXT_SW_DISABLE   (0)

Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV.

#define ANT_EXT_SW_ENABLE   (1)

Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV.

#define ANT_SEL_ANTENNA_0   (0)

Constant ANT_SEL_ANTENNA_0 for sub-register SR_ANT_SEL in register ANT_DIV.

#define ANT_SEL_ANTENNA_1   (1)

Constant ANT_SEL_ANTENNA_1 for sub-register SR_ANT_SEL in register ANT_DIV.

#define BATMON_HR_HIGH   (1)

Constant BATMON_HR_HIGH for sub-register SR_BATMON_HR in register BATMON.

#define BATMON_HR_LOW   (0)

Constant BATMON_HR_LOW for sub-register SR_BATMON_HR in register BATMON.

#define BATMON_NOT_VALID   (0)

Constant BATMON_NOT_VALID for sub-register SR_BATMON_OK in register BATMON.

#define BATMON_VALID   (1)

Constant BATMON_VALID for sub-register SR_BATMON_OK in register BATMON.

#define CCA_CH_BUSY   (0)

Constant CCA_CH_BUSY for sub-register SR_CCA_STATUS in register TRX_STATUS.

#define CCA_CH_IDLE   (1)

Constant CCA_CH_IDLE for sub-register SR_CCA_STATUS in register TRX_STATUS.

#define CCA_COMPLETED   (1)

Constant CCA_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS.

#define CCA_DETECTION_TIME_US   (135)
#define CCA_DURATION_SYM
Value:
(TAL_CONVERT_US_TO_SYMBOLS(CCA_DETECTION_TIME_US) + \
CCA_PROCESS_TIME_SYM)
CCA_PROCESS_TIME_SYM
#define CCA_PROCESS_TIME_SYM
Definition: avr2025_mac/source/tal/at86rf233/inc/at86rf233.h:108
TAL_CONVERT_US_TO_SYMBOLS
#define TAL_CONVERT_US_TO_SYMBOLS(time)
Conversion of microseconds to symbols.
Definition: tal.h:897
CCA_DETECTION_TIME_US
#define CCA_DETECTION_TIME_US
Definition: avr2025_mac/source/tal/at86rf233/inc/at86rf233.h:98
#define CCA_MODE_0   (0)

Constant CCA_MODE_0 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_MODE_1   (1)

Constant CCA_MODE_1 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_MODE_2   (2)

Constant CCA_MODE_2 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_MODE_3   (3)

Constant CCA_MODE_3 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_NO_START   (0)

Constant CCA_NO_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA.

#define CCA_ONGOING   (0)

Constant CCA_ONGOING for sub-register SR_CCA_DONE in register TRX_STATUS.

#define CCA_PRE_START_DURATION_US   (20)
#define CCA_PREPARATION_DURATION_US   (50)
#define CCA_PROCESS_TIME_SYM   (1)
#define CCA_START   (1)

Constant CCA_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA.

#define CLEAR_PD   (0)

Constant CLEAR_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1.

#define CLKM_16MHZ   (5)

Constant CLKM_16MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_1_16MHZ   (7)

Constant CLKM_1_16MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_1_4MHZ   (6)

Constant CLKM_1_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_1MHZ   (1)

Constant CLKM_1MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_2MHZ   (2)

Constant CLKM_2MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_4MHZ   (3)

Constant CLKM_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_8MHZ   (4)

Constant CLKM_8MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_NO_CLOCK   (0)

Constant CLKM_NO_CLOCK for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.

#define CLKM_SHA_DISABLE   (0)

Constant CLKM_SHA_DISABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0.

#define CLKM_SHA_ENABLE   (1)

Constant CLKM_SHA_ENABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0.

#define CRC16_NOT_VALID   (0)

Constant CRC16_NOT_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI.

#define CRC16_VALID   (1)

Constant CRC16_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI.

#define FLTR_RES_FT_DISABLE   (0)

Constant FLTR_RES_FT_DISABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1.

#define FLTR_RES_FT_ENABLE   (1)

Constant FLTR_RES_FT_ENABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1.

#define FRAME_VERSION_00   (0)

Constant FRAME_VERSION_00 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define FRAME_VERSION_01   (1)

Constant FRAME_VERSION_01 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define FRAME_VERSION_012   (2)

Constant FRAME_VERSION_012 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define FRAME_VERSION_IGNORED   (3)

Constant FRAME_VERSION_IGNORED for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define I_AM_COORD_DISABLE   (0)

Constant I_AM_COORD_DISABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1.

#define I_AM_COORD_ENABLE   (1)

Constant I_AM_COORD_ENABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1.

#define IRQ_HIGH_ACTIVE   (0)

Constant IRQ_HIGH_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1.

#define IRQ_LOW_ACTIVE   (1)

Constant IRQ_LOW_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1.

#define IRQ_MASK_MODE_OFF   (0)

Constant IRQ_MASK_MODE_OFF for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1.

#define IRQ_MASK_MODE_ON   (1)

Constant IRQ_MASK_MODE_ON for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1.

#define NORMAL   (0x0)

Constant NORMAL for sub-register SR_TST_CTRL_DIG in register TST_CTRL_DIGI.

#define OQPSK_SCRAM_DISABLE   (0)

Constant OQPSK_SCRAM_DISABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2.

#define OQPSK_SCRAM_ENABLE   (1)

Constant OQPSK_SCRAM_ENABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2.

#define P_ON_TO_CLKM_AVAILABLE_MAX_US   (1000)
#define P_ON_TO_CLKM_AVAILABLE_TYP_US   (330)
#define P_ON_TO_TRX_OFF_AFTER_CLKM_AVAILABLE_MAX_US   (1000)
#define P_ON_TO_TRX_OFF_AFTER_CLKM_AVAILABLE_TYP_US   (360)
#define PA_EXT_DISABLE   (0)

Constants.

Constant PA_EXT_disable for sub-register SR_PA_EXT_EN

#define PA_EXT_ENABLE   (1)

Constant PA_EXT_enable for sub-register SR_PA_EXT_EN.

#define PART_NUM_AT86RF233   (0x0B)

Constant PART_NUM_AT86RF233 for sub-register SR_PART_NUM in register PART_NUM.

Referenced by trx_init().

#define PLL_LOCK_DURATION_MAX_US   (250)

Referenced by switch_pll_on().

#define PRE_TX_DURATION_US   (32)
#define PROM_MODE_DISABLE   (0)

Constant PROM_MODE_DISABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1.

#define PROM_MODE_ENABLE   (1)

Constant PROM_MODE_ENABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1.

#define REG_BASE_ADDR   (0x00)

Register addresses.

Base address for Transceiver register address space

#define RG_AES_CTRL   (0x03)

Offset for register AES_CTRL.

#define RG_AES_CTRL_MIRROR   (0x14)

Offset for register AES_CTRL_MIRROR.

#define RG_AES_STATE_KEY_0   (0x04)

Offset for register AES_STATE_KEY_0.

#define RG_AES_STATUS   (0x02)

Offset for register AES_STATUS.

#define RG_ANT_DIV   (0x0D)

Offset for register ANT_DIV.

#define RG_BATMON   (0x11)

Offset for register BATMON.

#define RG_CC_CTRL_0   (0x13)

Offset for register CC_CTRL_0.

#define RG_CC_CTRL_1   (0x14)

Offset for register CC_CTRL_1.

#define RG_CCA_THRES   (0x09)

Offset for register CCA_THRES.

#define RG_CSMA_BE   (0x2F)

Offset for register CSMA_BE.

#define RG_CSMA_SEED_0   (0x2D)

Offset for register CSMA_SEED_0.

#define RG_CSMA_SEED_1   (0x2E)

Offset for register CSMA_SEED_1.

#define RG_ED   (0x01)

Offset for register ED.

#define RG_FTN_CTRL   (0x18)

Offset for register FTN_CTRL.

#define RG_IEEE_ADDR_0   (0x24)

Offset for register IEEE_ADDR_0.

#define RG_IEEE_ADDR_1   (0x25)

Offset for register IEEE_ADDR_1.

#define RG_IEEE_ADDR_2   (0x26)

Offset for register IEEE_ADDR_2.

#define RG_IEEE_ADDR_3   (0x27)

Offset for register IEEE_ADDR_3.

#define RG_IEEE_ADDR_4   (0x28)

Offset for register IEEE_ADDR_4.

#define RG_IEEE_ADDR_5   (0x29)

Offset for register IEEE_ADDR_5.

#define RG_IEEE_ADDR_6   (0x2A)

Offset for register IEEE_ADDR_6.

#define RG_IEEE_ADDR_7   (0x2B)

Offset for register IEEE_ADDR_7.

#define RG_IRQ_MASK   (0x0E)

Offset for register IRQ_MASK.

#define RG_IRQ_STATUS   (0x0F)

Offset for register IRQ_STATUS.

#define RG_LQI   (0x00)

Offset for register LQI.

#define RG_MAN_ID_0   (0x1E)

Offset for register MAN_ID_0.

#define RG_MAN_ID_1   (0x1F)

Offset for register MAN_ID_1.

#define RG_PAN_ID_0   (0x22)

Offset for register PAN_ID_0.

#define RG_PAN_ID_1   (0x23)

Offset for register PAN_ID_1.

#define RG_PART_NUM   (0x1C)

Offset for register PART_NUM.

#define RG_PHY_CC_CCA   (0x08)

Offset for register PHY_CC_CCA.

#define RG_PHY_ED_LEVEL   (0x07)

Offset for register PHY_ED_LEVEL.

#define RG_PHY_PMU_VALUE   (0x3B)

Offset for register PHY_PMU_VALUE.

#define RG_PHY_RSSI   (0x06)

Offset for register PHY_RSSI.

#define RG_PHY_TX_PWR   (0x05)

Offset for register PHY_TX_PWR.

#define RG_PLL_CF   (0x1A)

Offset for register PLL_CF.

#define RG_PLL_DCU   (0x1B)

Offset for register PLL_DCU.

#define RG_RX_CTRL   (0x0A)

Offset for register RX_CTRL.

#define RG_RX_STATUS   (0x02)

Offset for register RX_STATUS.

#define RG_RX_SYN   (0x15)

Offset for register RX_SYN.

#define RG_SFD_VALUE   (0x0B)

Offset for register SFD_VALUE.

#define RG_SHORT_ADDR_0   (0x20)

Offset for register SHORT_ADDR_0.

#define RG_SHORT_ADDR_1   (0x21)

Offset for register SHORT_ADDR_1.

#define RG_TRX_CTRL_0   (0x03)

Offset for register TRX_CTRL_0.

#define RG_TRX_CTRL_1   (0x04)

Offset for register TRX_CTRL_1.

#define RG_TRX_CTRL_2   (0x0C)

Offset for register TRX_CTRL_2.

#define RG_TRX_PAGE   (0x00)

Offset for register TRX_PAGE.

#define RG_TRX_RPC   (0x16)

Offset for register TRX_RPC.

Referenced by set_paramter_on_recptor_node(), tal_generate_rand_seed(), tal_rpc_mode_config(), and trx_config().

#define RG_TRX_STATE   (0x02)

Offset for register TRX_STATE.

#define RG_TRX_STATUS   (0x01)

Offset for register TRX_STATUS.

#define RG_TST_CTRL_DIGI   (0x36)

Offset for register TST_CTRL_DIGI.

#define RG_VERSION_NUM   (0x1D)

Offset for register VERSION_NUM.

#define RG_VREG_CTRL   (0x10)

Offset for register VREG_CTRL.

#define RG_XAH_CTRL_0   (0x2C)

Offset for register XAH_CTRL_0.

#define RG_XAH_CTRL_1   (0x17)

Offset for register XAH_CTRL_1.

#define RG_XAH_CTRL_2   (0x19)

Offset for register XAH_CTRL_2.

#define RG_XOSC_CTRL   (0x12)

Offset for register XOSC_CTRL.

#define RSSI_BASE_VAL_DBM   (-91)
#define RST_PULSE_WIDTH_NS   (625)

Typical timing values.

#define RST_PULSE_WIDTH_US   (10) /* ((RST_PULSE_WIDTH_NS + 999) / 1000) */
#define RX_BL_CTRL_DISABLE   (0)

Constant RX_BL_CTRL_DISABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1.

#define RX_BL_CTRL_ENABLE   (1)

Constant RX_BL_CTRL_ENABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1.

#define RX_DISABLE   (1)

Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.

#define RX_ENABLE   (0)

Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.

#define RX_OFFSET_16US   (3)

Constant RX_OFFSET_16US for sub-register SR_RX_RPC_CTRL in register TRX_RPC.

#define RX_OFFSET_MIN   (0)

Constant RX_OFFSET_MIN for sub-register SR_RX_RPC_CTRL in register TRX_RPC.

#define RX_SAFE_MODE_DISABLE   (0)

Constant RX_SAFE_MODE_DISABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2.

#define RX_SAFE_MODE_ENABLE   (1)

Constant RX_SAFE_MODE_ENABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2.

#define RX_TIMESTAMPING_DISABLE   (0)

Constant RX_TIMESTAMPING_DISABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1.

#define RX_TIMESTAMPING_ENABLE   (1)

Constant RX_TIMESTAMPING_ENABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1.

#define RXAPPENDIX_BASE_ADDR   (0x00)

Base address and size for RX frame appendix.

#define RXAPPENDIX_SIZE   (3)
#define SET_PD   (1)

Constant SET_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1.

#define SLEEP_TO_TRX_OFF_MAX_US   (1000)
#define SLEEP_TO_TRX_OFF_TYP_US   (210)
#define SPI_CMD_MODE_DEFAULT   (0)

Constant SPI_CMD_MODE_DEFAULT for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.

#define SPI_CMD_MODE_IRQ_STATUS   (3)

Constant SPI_CMD_MODE_IRQ_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.

#define SPI_CMD_MODE_PHY_RSSI   (2)

Constant SPI_CMD_MODE_PHY_RSSI for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.

#define SPI_CMD_MODE_TRX_STATUS   (1)

Constant SPI_CMD_MODE_TRX_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.

#define SR_AACK_ACK_TIME   0x17, 0x04, 2

Sub-register access.

Access parameters for sub-register AACK_ACK_TIME in register RG_XAH_CTRL_1

#define SR_AACK_DIS_ACK   0x2E, 0x10, 4

Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1.

#define SR_AACK_FLTR_RES_FT   0x17, 0x20, 5

Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1.

#define SR_AACK_FVN_MODE   0x2E, 0xC0, 6

Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.

#define SR_AACK_I_AM_COORD   0x2E, 0x08, 3

Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1.

#define SR_AACK_PROM_MODE   0x17, 0x02, 1

Access parameters for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1.

#define SR_AACK_SET_PD   0x2E, 0x20, 5

Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

#define SR_AACK_SPC_EN   0x17, 0x01, 0

Access parameters for sub-register AACK_SPC_EN in register RG_XAH_CTRL_1.

#define SR_AACK_UPLD_RES_FT   0x17, 0x10, 4

Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1.

#define SR_AES_DIR   0x03, 0x08, 3

Access parameters for sub-register AES_DIR in register RG_AES_CTRL.

#define SR_AES_DONE   0x02, 0x01, 0

Access parameters for sub-register AES_DONE in register RG_AES_STATUS.

#define SR_AES_ER   0x02, 0x80, 7

Access parameters for sub-register AES_ER in register RG_AES_STATUS.

#define SR_AES_MODE   0x03, 0x70, 4

Access parameters for sub-register AES_MODE in register RG_AES_CTRL.

#define SR_AES_REQUEST   0x03, 0x80, 7

Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL.

#define SR_ANT_CTRL   0x0D, 0x03, 0

Access parameters for sub-register ANT_CTRL in register RG_ANT_DIV.

#define SR_ANT_DIV_EN   0x0D, 0x08, 3

Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV.

#define SR_ANT_EXT_SW_EN   0x0D, 0x04, 2

Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV.

#define SR_ANT_SEL   0x0D, 0x80, 7

Access parameters for sub-register ANT_SEL in register RG_ANT_DIV.

#define SR_ARET_CSMA_RETRIES   0x19, 0x0E, 1

Access parameters for sub-register ARET_CSMA_RETRIES in register RG_XAH_CTRL_2.

#define SR_ARET_FRAME_RETRIES   0x19, 0xF0, 4

Access parameters for sub-register ARET_FRAME_RETRIES in register RG_XAH_CTRL_2.

#define SR_ARET_TX_TS_EN   0x17, 0x80, 7

Access parameters for sub-register ARET_TX_TS_EN in register RG_XAH_CTRL_1.

Referenced by trx_config().

#define SR_AVDD_OK   0x10, 0x40, 6

Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL.

#define SR_AVREG_EXT   0x10, 0x80, 7

Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL.

#define SR_BATMON_HR   0x11, 0x10, 4

Access parameters for sub-register BATMON_HR in register RG_BATMON.

#define SR_BATMON_OK   0x11, 0x20, 5

Access parameters for sub-register BATMON_OK in register RG_BATMON.

#define SR_BATMON_VTH   0x11, 0x0F, 0

Access parameters for sub-register BATMON_VTH in register RG_BATMON.

#define SR_CC_BAND   0x14, 0x0F, 0

Access parameters for sub-register CC_BAND in register RG_CC_CTRL_1.

#define SR_CC_NUMBER   0x13, 0xFF, 0

Access parameters for sub-register CC_NUMBER in register RG_CC_CTRL_0.

#define SR_CCA_DONE   0x01, 0x80, 7

Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS.

#define SR_CCA_ED_THRES   0x09, 0x0F, 0

Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES.

#define SR_CCA_MODE   0x08, 0x60, 5

Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA.

#define SR_CCA_REQUEST   0x08, 0x80, 7

Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA.

#define SR_CCA_STATUS   0x01, 0x40, 6

Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS.

#define SR_CHANNEL   0x08, 0x1F, 0

Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA.

#define SR_CLKM_CTRL   0x03, 0x07, 0

Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0.

#define SR_CLKM_SHA_SEL   0x03, 0x08, 3

Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0.

#define SR_CSMA_SEED_0   0x2D, 0xFF, 0

Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0.

#define SR_CSMA_SEED_1   0x2E, 0x07, 0

Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1.

#define SR_DVDD_OK   0x10, 0x04, 2

Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL.

#define SR_DVREG_EXT   0x10, 0x08, 3

Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL.

#define SR_ED_APX   0x01, 0xFF, 0

Access parameters for sub-register ED_APX in register RG_ED.

#define SR_ED_LEVEL   0x07, 0xFF, 0

Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL.

#define SR_FTN_START   0x18, 0x80, 7

Access parameters for sub-register FTN_START in register RG_FTN_CTRL.

#define SR_IEEE_ADDR_0   0x24, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0.

#define SR_IEEE_ADDR_1   0x25, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1.

#define SR_IEEE_ADDR_2   0x26, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2.

#define SR_IEEE_ADDR_3   0x27, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3.

#define SR_IEEE_ADDR_4   0x28, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4.

#define SR_IEEE_ADDR_5   0x29, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5.

#define SR_IEEE_ADDR_6   0x2A, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6.

#define SR_IEEE_ADDR_7   0x2B, 0xFF, 0

Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7.

#define SR_IPAN_RPC_EN   0x16, 0x02, 1

Access parameters for sub-register IPAN_RPC_EN in register RG_TRX_RPC.

#define SR_IRQ_0_PLL_LOCK   0x0F, 0x01, 0

Access parameters for sub-register IRQ_0_PLL_LOCK in register RG_IRQ_STATUS.

#define SR_IRQ_1_PLL_UNLOCK   0x0F, 0x02, 1

Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS.

#define SR_IRQ_2_EXT_EN   0x04, 0x40, 6

Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1.

#define SR_IRQ_2_RX_START   0x0F, 0x04, 2

Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS.

#define SR_IRQ_3_TRX_END   0x0F, 0x08, 3

Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS.

#define SR_IRQ_4_CCA_ED_DONE   0x0F, 0x10, 4

Access parameters for sub-register IRQ_4_CCA_ED_DONE in register RG_IRQ_STATUS.

#define SR_IRQ_5_AMI   0x0F, 0x20, 5

Access parameters for sub-register IRQ_5_AMI in register RG_IRQ_STATUS.

#define SR_IRQ_6_TRX_UR   0x0F, 0x40, 6

Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS.

#define SR_IRQ_7_BAT_LOW   0x0F, 0x80, 7

Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS.

#define SR_IRQ_MASK   0x0E, 0xFF, 0

Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK.

#define SR_IRQ_MASK_MODE   0x04, 0x02, 1

Access parameters for sub-register IRQ_MASK_MODE in register RG_TRX_CTRL_1.

#define SR_IRQ_POLARITY   0x04, 0x01, 0

Access parameters for sub-register IRQ_POLARITY in register RG_TRX_CTRL_1.

#define SR_LQI_APX   0x00, 0xFF, 0

Access parameters for sub-register LQI_APX in register RG_LQI.

#define SR_MAN_ID_0   0x1E, 0xFF, 0

Access parameters for sub-register MAN_ID_0 in register RG_MAN_ID_0.

#define SR_MAN_ID_1   0x1F, 0xFF, 0

Access parameters for sub-register MAN_ID_1 in register RG_MAN_ID_1.

#define SR_MAX_BE   0x2F, 0xF0, 4

Access parameters for sub-register MAX_BE in register RG_CSMA_BE.

#define SR_MAX_CSMA_RETRIES   0x2C, 0x0E, 1

Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0.

#define SR_MAX_FRAME_RETRIES   0x2C, 0xF0, 4

Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0.

#define SR_MIN_BE   0x2F, 0x0F, 0

Access parameters for sub-register MIN_BE in register RG_CSMA_BE.

#define SR_OQPSK_DATA_RATE   0x0C, 0x07, 0

Access parameters for sub-register OQPSK_DATA_RATE in register RG_TRX_CTRL_2.

#define SR_OQPSK_SCRAM_EN   0x0C, 0x20, 5

Access parameters for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2.

#define SR_PA_EXT_EN   0x04, 0x80, 7

Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1.

#define SR_PAN_ID_0   0x22, 0xFF, 0

Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0.

#define SR_PAN_ID_1   0x23, 0xFF, 0

Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1.

#define SR_PART_NUM   0x1C, 0xFF, 0

Access parameters for sub-register PART_NUM in register RG_PART_NUM.

#define SR_PDT_RPC_EN   0x16, 0x10, 4

Access parameters for sub-register PDT_RPC_EN in register RG_TRX_RPC.

#define SR_PDT_THRES   0x0A, 0x0F, 0

Access parameters for sub-register PDT_THRES in register RG_RX_CTRL.

#define SR_PLL_CF   0x1A, 0x0F, 0

Access parameters for sub-register PLL_CF in register RG_PLL_CF.

#define SR_PLL_CF_START   0x1A, 0x80, 7

Access parameters for sub-register PLL_CF_START in register RG_PLL_CF.

#define SR_PLL_DCU_START   0x1B, 0x80, 7

Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU.

#define SR_PLL_RPC_EN   0x16, 0x08, 3

Access parameters for sub-register PLL_RPC_EN in register RG_TRX_RPC.

#define SR_PMU_VALUE   0x3B, 0xFF, 0

Access parameters for sub-register PMU_VALUE in register RG_PHY_PMU_VALUE.

#define SR_RND_VALUE   0x06, 0x60, 5

Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI.

#define SR_RSSI   0x06, 0x1F, 0

Access parameters for sub-register RSSI in register RG_PHY_RSSI.

#define SR_RX_BL_CTRL   0x04, 0x10, 4

Access parameters for sub-register RX_BL_CTRL in register RG_TRX_CTRL_1.

#define SR_RX_CRC_VALID   0x06, 0x80, 7

Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI.

#define SR_RX_CRC_VALID_APX   0x02, 0x80, 7

Access parameters for sub-register RX_CRC_VALID_APX in register RG_RX_STATUS.

#define SR_RX_PDT_DIS   0x15, 0x80, 7

Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN.

#define SR_RX_PDT_LEVEL   0x15, 0x0F, 0

Access parameters for sub-register RX_PDT_LEVEL in register RG_RX_SYN.

#define SR_RX_RPC_CTRL   0x16, 0xC0, 6

Access parameters for sub-register RX_RPC_CTRL in register RG_TRX_RPC.

#define SR_RX_RPC_EN   0x16, 0x20, 5

Access parameters for sub-register RX_RPC_EN in register RG_TRX_RPC.

#define SR_RX_SAFE_MODE   0x0C, 0x80, 7

Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2.

#define SR_SFD_VALUE   0x0B, 0xFF, 0

Access parameters for sub-register SFD_VALUE in register RG_SFD_VALUE.

#define SR_SHORT_ADDR_0   0x20, 0xFF, 0

Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0.

#define SR_SHORT_ADDR_1   0x21, 0xFF, 0

Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1.

#define SR_SLOTTED_OPERATION   0x2C, 0x01, 0

Access parameters for sub-register SLOTTED_OPERATION in register RG_XAH_CTRL_0.

#define SR_SPI_CMD_MODE   0x04, 0x0C, 2

Access parameters for sub-register SPI_CMD_MODE in register RG_TRX_CTRL_1.

#define SR_TRAC_STATUS   0x02, 0xE0, 5

Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE.

#define SR_TRAC_STATUS_APX   0x02, 0x70, 4

Access parameters for sub-register TRAC_STATUS_APX in register RG_RX_STATUS.

#define SR_TRX_CMD   0x02, 0x1F, 0

Access parameters for sub-register TRX_CMD in register RG_TRX_STATE.

#define SR_TRX_STATUS   0x01, 0x1F, 0

Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS.

#define SR_TST_CTRL_DIG   0x36, 0x0F, 0

Access parameters for sub-register TST_CTRL_DIG in register RG_TST_CTRL_DIGI.

Referenced by tfa_continuous_tx_start().

#define SR_TX_AUTO_CRC_ON   0x04, 0x20, 5

Access parameters for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1.

#define SR_TX_PWR   0x05, 0x0F, 0

Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR.

#define SR_VERSION_NUM   0x1D, 0xFF, 0

Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM.

#define SR_XAH_TX_RPC_EN   0x16, 0x04, 2

Access parameters for sub-register XAH_TX_RPC_EN in register RG_TRX_RPC.

#define SR_XTAL_MODE   0x12, 0xF0, 4

Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL.

#define SR_XTAL_TRIM   0x12, 0x0F, 0

Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL.

#define T_OCT_US   (32)
#define T_SYM_US   (16)
#define THRES_ANT_DIV_DISABLE   (0x7)

Constant THRES_ANT_DIV_DISABLE for sub-register SR_PDT_THRES in register RX_CTRL.

#define THRES_ANT_DIV_ENABLE   (0x3)

Constant THRES_ANT_DIV_ENABLE for sub-register SR_PDT_THRES in register RX_CTRL.

#define TRANSCEIVER_NAME   "AT86RF233"
#define TRX_IRQ_DELAY_US   (9)
#define TRX_OFF_TO_PLL_ON_TIME_US   (80)
#define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES   (35)
#define TRX_SUPPORTED_CHANNELS   (0x07FFF800)

Parameter definitions.

Important parameters.

#define TST_CONT_TX   (0xF)

Constant TST_CONT_TX for sub-register SR_TST_CTRL_DIG in register TST_CTRL_DIGI.

Referenced by tfa_continuous_tx_start().

#define TX_ARET_TIMESTAMPING_DISABLE   (0)

Constant TX_ARET_TIMESTAMPING_DISABLE for sub-register SR_ARET_TX_TS_EN in register XAH_CTRL_1.

#define TX_ARET_TIMESTAMPING_ENABLE   (1)

Constant TX_ARET_TIMESTAMPING_ENABLE for sub-register SR_ARET_TX_TS_EN in register XAH_CTRL_1.

Referenced by trx_config().

#define TX_AUTO_CRC_DISABLE   (0)

Constant TX_AUTO_CRC_DISABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1.

#define TX_AUTO_CRC_ENABLE   (1)

Constant TX_AUTO_CRC_ENABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1.

#define TX_PWR_TOLERANCE   (0x80)
#define UPLD_RES_FT_DISABLE   (0)

Constant UPLD_RES_FT_DISABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1.

#define UPLD_RES_FT_ENABLE   (1)

Constant UPLD_RES_FT_ENABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1.

#define VERSION_NUM_AT86RF233   (0x01)

Constant VERSION_NUM_AT86RF233 for sub-register SR_VERSION_NUM in register VERSION_NUM.

typedef enum tal_trx_status_tag tal_trx_status_t

sub-register TRX_STATUS in register TRX_STATUS

typedef enum trx_cmd_tag trx_cmd_t

Enumerations.

sub-register TRX_CMD in register TRX_STATE

typedef enum trx_irq_reason_tag trx_irq_reason_t

sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS

typedef enum trx_trac_status_tag trx_trac_status_t

sub-register TRAC_STATUS in register TRX_STATE

enum tal_trx_status_tag

sub-register TRX_STATUS in register TRX_STATUS

Enumerator
P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

RX_ON_NOCLK 

Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.

RX_AACK_ON_NOCLK 

Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.

BUSY_RX_AACK_NOCLK 

Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant TRX_SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

RX_ON_NOCLK 

Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.

RX_AACK_ON_NOCLK 

Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.

BUSY_RX_AACK_NOCLK 

Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant TRX_SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

RX_ON_NOCLK 

Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.

RX_AACK_ON_NOCLK 

Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.

BUSY_RX_AACK_NOCLK 

Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant TRX_SLEEP for sub-register SR_TRX_STATUS.

PREP_DEEP_SLEEP 

Constant PREP_DEEP_SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

TRX_DEEP_SLEEP 

Software implemented state.

P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant TRX_SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

enum trx_cmd_tag

Enumerations.

sub-register TRX_CMD in register TRX_STATE

Enumerator
CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_PREP_DEEP_SLEEP 

Constant CMD_PREP_DEEP_SLEEP for sub-register SR_TRX_CMD.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

CMD_DEEP_SLEEP 

Software implemented command.

CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

enum trx_irq_reason_tag

sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS

Enumerator
TRX_NO_IRQ 

No interrupt is indicated by IRQ_STATUS register.

TRX_IRQ_PLL_LOCK 

PLL goes to lock-state.

TRX_IRQ_PLL_UNLOCK 

Signals an unlocked PLL.

TRX_IRQ_RX_START 

Signals begin of a receiving frame.

TRX_IRQ_TRX_END 

Signals end of frames (transmit and receive)

TRX_IRQ_CCA_ED_READY 

Multi-functional interrupt: AWAKE_END: Indicates that the radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states.

CCA_ED_READY: Signals the end of a CCA or ED measurement.

TRX_IRQ_AMI 

Signals an address match.

TRX_IRQ_TRX_UR 

Signals a FIFO underrun.

TRX_IRQ_BAT_LOW 

Signals low battery.

TRX_IRQ_7_BAT_LOW 

Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.

TRX_IRQ_6_TRX_UR 

Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.

TRX_IRQ_5_AMI 

Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.

TRX_IRQ_4_CCA_ED_DONE 

Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.

TRX_IRQ_3_TRX_END 

Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.

TRX_IRQ_2_RX_START 

Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.

TRX_IRQ_1_PLL_UNLOCK 

Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.

TRX_IRQ_0_PLL_LOCK 

Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.

TRX_NO_IRQ 

No interrupt is indicated by IRQ_STATUS register.

TRX_IRQ_7_BAT_LOW 

Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.

TRX_IRQ_6_TRX_UR 

Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.

TRX_IRQ_5_AMI 

Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.

TRX_IRQ_4_CCA_ED_DONE 

Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.

TRX_IRQ_3_TRX_END 

Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.

TRX_IRQ_2_RX_START 

Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.

TRX_IRQ_1_PLL_UNLOCK 

Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.

TRX_IRQ_0_PLL_LOCK 

Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.

TRX_NO_IRQ 

No interrupt is indicated by IRQ_STATUS register.

TRX_IRQ_7_BAT_LOW 

Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.

TRX_IRQ_6_TRX_UR 

Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.

TRX_IRQ_5_AMI 

Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.

TRX_IRQ_4_CCA_ED_DONE 

Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.

TRX_IRQ_3_TRX_END 

Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.

TRX_IRQ_2_RX_START 

Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.

TRX_IRQ_1_PLL_UNLOCK 

Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.

TRX_IRQ_0_PLL_LOCK 

Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.

TRX_NO_IRQ 

No interrupt is indicated by IRQ_STATUS register.

TRX_IRQ_7_BAT_LOW 

Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.

TRX_IRQ_6_TRX_UR 

Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.

TRX_IRQ_5_AMI 

Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.

TRX_IRQ_4_CCA_ED_DONE 

Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.

TRX_IRQ_3_TRX_END 

Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.

TRX_IRQ_2_RX_START 

Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.

TRX_IRQ_1_PLL_UNLOCK 

Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.

TRX_IRQ_0_PLL_LOCK 

Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.

TRX_NO_IRQ 

No interrupt is indicated by IRQ_STATUS register.

enum trx_trac_status_tag

sub-register TRAC_STATUS in register TRX_STATE

Enumerator
TRAC_SUCCESS 
TRAC_SUCCESS_DATA_PENDING 
TRAC_WAIT_FOR_ACK 
TRAC_CHANNEL_ACCESS_FAILURE 
TRAC_NO_ACK 
TRAC_INVALID 
TRAC_SUCCESS 

Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_DATA_PENDING 

Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_WAIT_FOR_ACK 

Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.

TRAC_CHANNEL_ACCESS_FAILURE 

Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.

TRAC_NO_ACK 

Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.

TRAC_INVALID 

Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS 

Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_DATA_PENDING 

Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_WAIT_FOR_ACK 

Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.

TRAC_CHANNEL_ACCESS_FAILURE 

Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.

TRAC_NO_ACK 

Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.

TRAC_INVALID 

Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS 

Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_DATA_PENDING 

Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_WAIT_FOR_ACK 

Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.

TRAC_CHANNEL_ACCESS_FAILURE 

Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.

TRAC_NO_ACK 

Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.

TRAC_INVALID 

Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS 

Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_DATA_PENDING 

Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_WAIT_FOR_ACK 

Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.

TRAC_CHANNEL_ACCESS_FAILURE 

Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.

TRAC_NO_ACK 

Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.

TRAC_INVALID 

Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.

Generated on Fri Mar 4 2022 23:25:59 for SAMD21 by   doxygen 1.8.5