The AT86RF233 is a feature rich, low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate sub 1GHz ISM band applications Refer AT86RF233 Data Sheet for detailed information .
#define AACK_FLTR_RES_FT 5 |
#define AACK_I_AM_COORD 3 |
#define AACK_UPLD_RES_FT 4 |
#define AES_BLOCK_SIZE 16 |
#define AES_CORE_CYCLE_TIME 24 /* us */ |
#define AES_CTRL_M_REG 0x94 |
#define AES_CTRL_REG 0x83 |
#define AES_CTRL_REQUEST 7 |
#define AES_STATE_REG 0x84 |
#define AES_STATUS_DONE 0 |
#define AES_STATUS_REG 0x82 |
#define ARET_CSMA_RETRIES 1 |
#define ARET_FRAME_RETRIES 4 |
#define CCA_THRES_REG 0x09 |
#define CSMA_SEED_0_REG 0x2d |
#define CSMA_SEED_1_REG 0x2e |
#define FTN_CTRL_REG 0x18 |
#define IEEE_ADDR_0_REG 0x24 |
#define IEEE_ADDR_1_REG 0x25 |
#define IEEE_ADDR_2_REG 0x26 |
#define IEEE_ADDR_3_REG 0x27 |
#define IEEE_ADDR_4_REG 0x28 |
#define IEEE_ADDR_5_REG 0x29 |
#define IEEE_ADDR_6_REG 0x2a |
#define IEEE_ADDR_7_REG 0x2b |
#define IRQ_MASK_REG 0x0e |
#define IRQ_STATUS_REG 0x0f |
#define MAN_ID_0_REG 0x1e |
#define MAN_ID_1_REG 0x1f |
#define MAX_CSMA_RETRES 1 |
#define MAX_FRAME_RETRES 4 |
#define OQPSK_DATA_RATE 0 |
#define PAN_ID_0_REG 0x22 |
#define PAN_ID_1_REG 0x23 |
#define PART_NUM_REG 0x1c |
#define PEL_SHIFT_VALUE 6 |
#define PHY_CC_CCA_REG 0x08 |
#define PHY_ED_LEVEL_REG 0x07 |
#define PHY_HAS_AES_MODULE |
#define PHY_HAS_RANDOM_NUMBER_GENERATOR |
#define PHY_PMU_VALUE_REG 0x3b |
#define PHY_RSSI_BASE_VAL (-91) |
#define PHY_RSSI_REG 0x06 |
#define PHY_TX_PWR_REG 0x05 |
#define PHY_TX_TIME_REG 0x3b |
#define RANDOM_NUMBER_UPDATE_INTERVAL 1 /* us */ |
#define RF_CMD_FRAME_R ((0 << 7) | (0 << 6) | (1 << 5)) |
#define RF_CMD_FRAME_W ((0 << 7) | (1 << 6) | (1 << 5)) |
#define RF_CMD_REG_R ((1 << 7) | (0 << 6)) |
#define RF_CMD_REG_W ((1 << 7) | (1 << 6)) |
#define RF_CMD_SRAM_R ((0 << 7) | (0 << 6) | (0 << 5)) |
#define RF_CMD_SRAM_W ((0 << 7) | (1 << 6) | (0 << 5)) |
#define SFD_VALUE_REG 0x0b |
#define SHORT_ADDR_0_REG 0x20 |
#define SHORT_ADDR_1_REG 0x21 |
#define SLOTTED_OPERATION 0 |
#define TRAC_STATUS_CHANNEL_ACCESS_FAILURE 3 |
#define TRAC_STATUS_INVALID 7 |
#define TRAC_STATUS_NO_ACK 5 |
#define TRAC_STATUS_SUCCESS 0 |
#define TRAC_STATUS_SUCCESS_DATA_PENDING 1 |
#define TRAC_STATUS_SUCCESS_WAIT_FOR_ACK 2 |
#define TRX_CMD_FORCE_PLL_ON 4 |
#define TRX_CMD_FORCE_TRX_OFF 3 |
#define TRX_CMD_RX_AACK_ON 22 |
#define TRX_CMD_TRX_OFF 8 |
#define TRX_CMD_TX_ARET_ON 25 |
#define TRX_CMD_TX_START 2 |
#define TRX_CTRL_0_REG 0x03 |
#define TRX_CTRL_1_REG 0x04 |
#define TRX_CTRL_2_REG 0x0c |
#define TRX_STATE_REG 0x02 |
#define TRX_STATUS_BUSY_RX 1 |
#define TRX_STATUS_BUSY_RX_AACK 17 |
#define TRX_STATUS_BUSY_RX_AACK_NOCLK 30 |
#define TRX_STATUS_BUSY_TX 2 |
#define TRX_STATUS_BUSY_TX_ARET 18 |
#define TRX_STATUS_MASK 0x1f |
#define TRX_STATUS_P_ON 0 |
#define TRX_STATUS_PLL_ON 9 |
#define TRX_STATUS_REG 0x01 |
#define TRX_STATUS_RX_AACK_ON 22 |
#define TRX_STATUS_RX_AACK_ON_NOCLK 29 |
#define TRX_STATUS_RX_ON 6 |
#define TRX_STATUS_RX_ON_NOCLK 28 |
#define TRX_STATUS_SLEEP 15 |
#define TRX_STATUS_STATE_TRANSITION 31 |
#define TRX_STATUS_TRX_OFF 8 |
#define TRX_STATUS_TX_ARET_ON 25 |
#define TST_CTRL_DIGI_REG 0x36 |
#define VERSION_NUM_REG 0x1d |
#define VREG_CTRL_REG 0x10 |
#define XAH_CTRL_0_REG 0x2c |
#define XAH_CTRL_1_REG 0x17 |
#define XAH_CTRL_2_REG 0x19 |
#define XOSC_CTRL_REG 0x12 |
Enumerator |
---|
PHY_STATUS_SUCCESS |
|
PHY_STATUS_CHANNEL_ACCESS_FAILURE |
|
PHY_STATUS_NO_ACK |
|
PHY_STATUS_ERROR |
|
void PHY_DataConf |
( |
uint8_t |
status | ) |
|
References PHY_DataInd_t::data, NwkFrame_t::data, PHY_DataInd_t::lqi, NULL, NWK_RX_STATE_RECEIVED, nwkFrameAlloc(), PHY_DataInd_t::rssi, NwkFrame_t::rx, PHY_DataInd_t::size, NwkFrame_t::size, and NwkFrame_t::state.
void PHY_DataReq |
( |
uint8_t * |
data | ) |
|
int8_t PHY_EdReq |
( |
void |
| ) |
|
void PHY_EncryptReq |
( |
uint8_t * |
text, |
|
|
uint8_t * |
key |
|
) |
| |
References IRQ_MASK_MODE, OQPSK_SCRAM_EN, PHY_STATE_IDLE, PHY_TX_PWR_REG, phyBand, phyModulation, phyReadRegister(), PhyReset(), phyRxState, phyState, phyWriteRegister(), RF_CTRL_0_REG, RX_SAFE_MODE, SPI_CMD_MODE, TRX_CMD_TRX_OFF, TRX_CTRL_1_REG, TRX_CTRL_2_REG, trx_spi_init(), TRX_STATE_REG, TRX_STATUS_MASK, TRX_STATUS_REG, TRX_STATUS_TRX_OFF, and TX_AUTO_CRC_ON.
Referenced by SYS_Init().
uint16_t PHY_RandomReq |
( |
void |
| ) |
|
void PHY_SetChannel |
( |
uint8_t |
channel | ) |
|
void PHY_SetIEEEAddr |
( |
uint8_t * |
ieee_addr | ) |
|
void PHY_SetPanId |
( |
uint16_t |
panId | ) |
|
void PHY_SetRxState |
( |
bool |
rx | ) |
|
void PHY_SetShortAddr |
( |
uint16_t |
addr | ) |
|
void PHY_SetTxPower |
( |
uint8_t |
txPower | ) |
|
void PHY_TaskHandler |
( |
void |
| ) |
|
References PHY_DataInd_t::data, IRQ_STATUS_REG, PHY_DataInd_t::lqi, PHY_CRC_SIZE, PHY_DataConf(), PHY_DataInd(), PHY_ED_LEVEL_REG, PHY_RSSI_BASE_VAL, PHY_STATE_IDLE, PHY_STATE_SLEEP, PHY_STATE_TX_WAIT_END, PHY_STATUS_CHANNEL_ACCESS_FAILURE, PHY_STATUS_ERROR, PHY_STATUS_NO_ACK, PHY_STATUS_SUCCESS, phyReadRegister(), phyRssiBaseVal(), phyRxBuffer, phySetRxState(), phyState, phyWaitState(), PHY_DataInd_t::rssi, PHY_DataInd_t::size, status, TRAC_STATUS, TRAC_STATUS_CHANNEL_ACCESS_FAILURE, TRAC_STATUS_NO_ACK, TRAC_STATUS_SUCCESS, TRX_END, trx_frame_read(), TRX_STATE_REG, and TRX_STATUS_RX_AACK_ON.
Referenced by SYS_TaskHandler().