Macros | |
#define | AACK_PROM_MODE (1 << 1) |
#define | AES_ADDR_HI (0x94) |
#define | AES_ADDR_LO (0x82) |
#define | BPSK_20 (0x00) |
#define | BPSK_40 (0x04) |
#define | FRAME_BUFFER_ACCESS (1 << 5) |
#define | FRAMEBUF_ADDR_HI (0x7F) /* ie the trx-fifo is 128B long */ |
#define | FRAMEBUF_ADDR_LO (0x00) |
#define | IRQ_AMI (1 << 5) /* address matching on rx */ |
#define | IRQ_BAT_LOW (1 << 7) |
#define | IRQ_CCA_ED_DONE (1 << 4) /* CCA or ED is done */ |
#define | IRQ_FRAME_RX_START IRQ_RX_START /* synonym */ |
#define | IRQ_PLL_LOCK (1 << 0) |
#define | IRQ_PLL_UNLOCK (1 << 1) |
#define | IRQ_RX_ADDRESS_MATCH IRQ_AMI /* synonym */ |
#define | IRQ_RX_START (1 << 2) /* frame rx started, frame len can be read from fifo[0] */ |
#define | IRQ_TRX_DONE IRQ_TRX_END /* synonym */ |
#define | IRQ_TRX_END (1 << 3) /* frame tx or rx complete */ |
#define | IRQ_TRX_UR (1 << 6) /* frame buffer violation */ |
#define | IRQ_TRXBUF_ACCESS_VIOLATION IRQ_TRX_UR /* synonym */ |
#define | OQPSK_RC_250 (0x1C) |
#define | OQPSK_SIN_250 (0x0C) |
#define | OQPSK_SIN_RC_100 (0x08) |
#define | PHY_CC_CCA_CHANNEL (0x1F) |
#define | PHY_CC_CCA_DO_CCA (1 << 7) /* starts manual CCA */ |
#define | PHY_CC_CCA_MODE_CS (2 << 5) |
#define | PHY_CC_CCA_MODE_CS_AND_ED (3 << 5) |
#define | PHY_CC_CCA_MODE_CS_OR_ED (0 << 5) |
#define | PHY_CC_CCA_MODE_ED (1 << 5) |
#define | PHY_RSSI_CRC_VALID (1 << 7) /* FCS/CRC valid if set */ |
#define | PHY_RSSI_RNG (0x60) /* two-bit RNG */ |
#define | PHY_RSSI_RSSI (0x1F) /* RSSI measurement */ |
#define | PHY_TX_PWR_TXP (0x0F) |
#define | PLL_CF_DO_MANUAL_CAL (0xD7) /* to do manual calibration, write this value to the reg (includes defaults) */ |
#define | PLL_CF_START_CAL (1 << 7) /* start manual calibration; reads one until done */ |
#define | READ_ACCESS (0 << 6) |
#define | REGISTER_ACCESS (1 << 7) |
#define | RF212_REG_ADDR_MAX (0x3D) /* highest register address */ |
#define | RF212_REG_ADDR_MIN (0x00) /* lowest register address */ |
#define | RF212_REG_ANT_DIV (0x0D) |
#define | RF212_REG_BATMON (0x11) |
#define | RF212_REG_CC_CTRL_0 (0x13) |
#define | RF212_REG_CC_CTRL_1 (0x14) |
#define | RF212_REG_CCA_THRES (0x09) |
#define | RF212_REG_CSMA_BE (0x2F) |
#define | RF212_REG_CSMA_SEED_0 (0x2D) |
#define | RF212_REG_CSMA_SEED_1 (0x2E) |
#define | RF212_REG_FTN_CTRL (0x18) |
#define | RF212_REG_IEEE_ADDR_0 (0x24) |
#define | RF212_REG_IEEE_ADDR_1 (0x25) |
#define | RF212_REG_IEEE_ADDR_2 (0x26) |
#define | RF212_REG_IEEE_ADDR_3 (0x27) |
#define | RF212_REG_IEEE_ADDR_4 (0x28) |
#define | RF212_REG_IEEE_ADDR_5 (0x29) |
#define | RF212_REG_IEEE_ADDR_6 (0x2A) |
#define | RF212_REG_IEEE_ADDR_7 (0x2B) |
#define | RF212_REG_IRQ_MASK (0x0E) |
#define | RF212_REG_IRQ_STATUS (0x0F) /* reading this also clears it */ |
#define | RF212_REG_MAN_ID_0 (0x1E) |
#define | RF212_REG_MAN_ID_1 (0x1F) |
#define | RF212_REG_PAN_ID_0 (0x22) |
#define | RF212_REG_PAN_ID_1 (0x23) |
#define | RF212_REG_PART_NUM (0x1C) |
#define | RF212_REG_PHY_CC_CCA (0x08) |
#define | RF212_REG_PHY_ED_LEVEL (0x07) |
#define | RF212_REG_PHY_RSSI (0x06) |
#define | RF212_REG_PHY_TX_PWR (0x05) |
#define | RF212_REG_PHY_TX_TIME (0x3B) |
#define | RF212_REG_PLL_CF (0x1A) |
#define | RF212_REG_PLL_DCU (0x1B) |
#define | RF212_REG_RX_CTRL (0x0A) |
#define | RF212_REG_RX_SYN (0x15) |
#define | RF212_REG_SFD_VALUE (0x0B) |
#define | RF212_REG_SHORT_ADDR_0 (0x20) |
#define | RF212_REG_SHORT_ADDR_1 (0x21) |
#define | RF212_REG_TRX_CTRL_0 (0x03) |
#define | RF212_REG_TRX_CTRL_1 (0x04) |
#define | RF212_REG_TRX_CTRL_2 (0x0C) |
#define | RF212_REG_TRX_RPC (0x16) |
#define | RF212_REG_TRX_STATE (0x02) |
#define | RF212_REG_TRX_STATUS (0x01) |
#define | RF212_REG_TST_AGC (0x3C) |
#define | RF212_REG_TST_CTRL_DIGI (0x36) |
#define | RF212_REG_TST_SDM (0x3D) |
#define | RF212_REG_VERSION_NUM (0x1D) |
#define | RF212_REG_VREG_CTRL (0x10) |
#define | RF212_REG_XAH_CTRL_0 (0x2C) |
#define | RF212_REG_XAH_CTRL_1 (0x17) |
#define | RF212_REG_XAH_CTRL_2 (0x19) |
#define | RF212_REG_XOSC_CTRL (0x12) |
#define | RX_DISABLE (1) |
Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More... | |
#define | RX_ENABLE (0) |
Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More... | |
#define | RX_STATUS_CRC_OK (1 << 7) /* CRC/FCS */ |
#define | RX_STATUS_TRAC_STATUS (0x70) |
#define | SR_MAX_CSMA_RETRIES 0x2C, 0X0E, 1 |
#define | SR_MAX_FRAME_RETRIES 0x2C, 0xF0, 4 |
#define | SR_RND_VALUE 0x06, 0x60, 5 |
Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI. More... | |
#define | SR_RX_PDT_DIS 0x15, 0x80, 7 |
Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN. More... | |
#define | SRAM_ACCESS (0 << 5) |
#define | STATE_BUSY_RX (0x01) |
#define | STATE_BUSY_RX_AACK (0x11) |
#define | STATE_BUSY_TX (0x02) /* 7.2 - 13.8 mA */ |
#define | STATE_BUSY_TX_ARET (0x12) |
#define | STATE_P_ON (0x00) |
#define | STATE_PLL_ON (0x09) /* 5.2 mA */ |
#define | STATE_PREP_DEEP_SLEEP (0x10) |
#define | STATE_RX_AACK_ON (0x16) |
#define | STATE_RX_ON (0x06) /* 11.8 mA */ |
#define | STATE_SLEEP (0x0F) /* 0.2 uA */ |
#define | STATE_TRANSITION (0x1F) |
#define | STATE_TRX_OFF (0x08) /* 300 uA */ |
#define | STATE_TX_ARET_ON (0x19) |
#define | TRAC_CHANNEL_ACCESS_FAIL (3 << 5) |
#define | TRAC_INVALID (7 << 5) |
#define | TRAC_NO_ACK (5 << 5) |
#define | TRAC_SUCCESS (0 << 5) |
#define | TRAC_SUCCESS_DATA_PENDING (1 << 5) |
#define | TRAC_SUCCESS_WAIT_FOR_ACK (2 << 5) |
#define | TRX_BUFFER_LENGTH 128 /* bytes */ |
#define | TRX_CCA_DONE (1 << 7) |
#define | TRX_CCA_STATUS (1 << 6) |
#define | TRX_CTRL_1_AUTO_CRC (1 << 5) |
#define | TRX_CTRL_1_DIG2_TIMESTAMPING (1 << 6) /* pin DIG2 goes high ca 200us after SFD finished */ |
#define | TRX_CTRL_1_DIG34_RXTX_INDICATOR TRX_CTRL_1_PA_EXT_EN /* synonym */ |
#define | TRX_CTRL_1_FRAME_BUF_EMPTY_EN (1 << 4) /* IRQ pin turns into indicator during frame buffer reads */ |
#define | TRX_CTRL_1_IRQ_MASK_MODE (1 << 1) /* irqs shown in IRQ_STATUS even if not in IRQ_MASK */ |
#define | TRX_CTRL_1_IRQ_POL_ACTIVE_LOW (1 << 0) |
#define | TRX_CTRL_1_PA_EXT_EN (1 << 7) /* pin DIG3/DIG4 indicates tx/rx mode */ |
#define | TRX_CTRL_1_SPI_CMD_IRQ_STATUS (3 << 2) |
#define | TRX_CTRL_1_SPI_CMD_RSSI (2 << 2) |
#define | TRX_CTRL_1_SPI_CMD_TRX_STATUS (1 << 2) |
#define | TRX_CTRL_2_RX_SAFE_MODE (1 << 7) /* disallow rx buffer overwrites */ |
#define | TRX_STATE_TRAC_STATUS (0xE0) /* result of transaction in extended mode */ |
#define | TRX_STATE_TRX_COMMAND (0x1F) |
#define | TRX_STATUS (0x1F) /* radio status bit field */ |
#define | TRXCMD_FORCE_PLL_ON (0x04) |
#define | TRXCMD_FORCE_TRX_OFF (0x03) |
#define | TRXCMD_NOP (0x00) |
#define | TRXCMD_PLL_ON (0x09) |
#define | TRXCMD_PREP_DEEP_SLEEP (0x10) |
#define | TRXCMD_RX_AACK_ON (0x16) |
#define | TRXCMD_RX_ON (0x06) |
#define | TRXCMD_TRX_OFF (0x08) |
#define | TRXCMD_TX_ARET_ON (0x19) |
#define | TRXCMD_TX_START (0x02) |
#define | TXP_0 (0x07) |
#define | TXP_1 (0x06) |
#define | TXP_2 (0x05) |
#define | TXP_2P5 (0x04) |
#define | TXP_3 (0x03) |
#define | TXP_3P4 (0x02) |
#define | TXP_3P7 (0x01) |
#define | TXP_4 (0x00) |
#define | TXP_M1 (0x08) |
#define | TXP_M12 (0x0E) |
#define | TXP_M17 (0x0F) |
#define | TXP_M2 (0x09) |
#define | TXP_M3 (0x0A) |
#define | TXP_M4 (0x0B) |
#define | TXP_M6 (0x0C) |
#define | TXP_M8 (0x0D) |
#define | WRITE_ACCESS (1 << 6) |
#define AACK_PROM_MODE (1 << 1) |
#define AES_ADDR_HI (0x94) |
#define AES_ADDR_LO (0x82) |
#define BPSK_20 (0x00) |
#define BPSK_40 (0x04) |
#define FRAME_BUFFER_ACCESS (1 << 5) |
#define FRAMEBUF_ADDR_HI (0x7F) /* ie the trx-fifo is 128B long */ |
#define FRAMEBUF_ADDR_LO (0x00) |
#define IRQ_AMI (1 << 5) /* address matching on rx */ |
#define IRQ_BAT_LOW (1 << 7) |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define IRQ_CCA_ED_DONE (1 << 4) /* CCA or ED is done */ |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define IRQ_FRAME_RX_START IRQ_RX_START /* synonym */ |
#define IRQ_PLL_LOCK (1 << 0) |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define IRQ_PLL_UNLOCK (1 << 1) |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define IRQ_RX_ADDRESS_MATCH IRQ_AMI /* synonym */ |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define IRQ_TRX_DONE IRQ_TRX_END /* synonym */ |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define IRQ_TRX_END (1 << 3) /* frame tx or rx complete */ |
#define IRQ_TRX_UR (1 << 6) /* frame buffer violation */ |
#define IRQ_TRXBUF_ACCESS_VIOLATION IRQ_TRX_UR /* synonym */ |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define OQPSK_RC_250 (0x1C) |
#define OQPSK_SIN_250 (0x0C) |
#define OQPSK_SIN_RC_100 (0x08) |
#define PHY_CC_CCA_CHANNEL (0x1F) |
Referenced by rf_get_channel(), and rf_set_channel().
#define PHY_CC_CCA_DO_CCA (1 << 7) /* starts manual CCA */ |
Referenced by rf212_channel_clear(), and rf233_channel_clear().
#define PHY_CC_CCA_MODE_CS (2 << 5) |
#define PHY_CC_CCA_MODE_CS_AND_ED (3 << 5) |
#define PHY_CC_CCA_MODE_CS_OR_ED (0 << 5) |
Referenced by rf212_channel_clear(), and rf233_channel_clear().
#define PHY_CC_CCA_MODE_ED (1 << 5) |
#define PHY_RSSI_CRC_VALID (1 << 7) /* FCS/CRC valid if set */ |
#define PHY_RSSI_RNG (0x60) /* two-bit RNG */ |
#define PHY_RSSI_RSSI (0x1F) /* RSSI measurement */ |
#define PHY_TX_PWR_TXP (0x0F) |
Referenced by rf212_get_txp(), and rf233_get_txp().
#define PLL_CF_DO_MANUAL_CAL (0xD7) /* to do manual calibration, write this value to the reg (includes defaults) */ |
#define PLL_CF_START_CAL (1 << 7) /* start manual calibration; reads one until done */ |
#define READ_ACCESS (0 << 6) |
#define REGISTER_ACCESS (1 << 7) |
#define RF212_REG_ADDR_MAX (0x3D) /* highest register address */ |
#define RF212_REG_ADDR_MIN (0x00) /* lowest register address */ |
#define RF212_REG_ANT_DIV (0x0D) |
#define RF212_REG_BATMON (0x11) |
#define RF212_REG_CC_CTRL_0 (0x13) |
#define RF212_REG_CC_CTRL_1 (0x14) |
#define RF212_REG_CCA_THRES (0x09) |
#define RF212_REG_CSMA_BE (0x2F) |
#define RF212_REG_CSMA_SEED_0 (0x2D) |
#define RF212_REG_CSMA_SEED_1 (0x2E) |
#define RF212_REG_FTN_CTRL (0x18) |
#define RF212_REG_IEEE_ADDR_0 (0x24) |
#define RF212_REG_IEEE_ADDR_1 (0x25) |
#define RF212_REG_IEEE_ADDR_2 (0x26) |
#define RF212_REG_IEEE_ADDR_3 (0x27) |
#define RF212_REG_IEEE_ADDR_4 (0x28) |
#define RF212_REG_IEEE_ADDR_5 (0x29) |
#define RF212_REG_IEEE_ADDR_6 (0x2A) |
#define RF212_REG_IEEE_ADDR_7 (0x2B) |
#define RF212_REG_IRQ_MASK (0x0E) |
Referenced by rf212_init().
#define RF212_REG_IRQ_STATUS (0x0F) /* reading this also clears it */ |
Referenced by rf212_init(), rf212_interrupt_poll(), and rf_generate_random_seed().
#define RF212_REG_MAN_ID_0 (0x1E) |
#define RF212_REG_MAN_ID_1 (0x1F) |
#define RF212_REG_PAN_ID_0 (0x22) |
#define RF212_REG_PAN_ID_1 (0x23) |
#define RF212_REG_PART_NUM (0x1C) |
#define RF212_REG_PHY_CC_CCA (0x08) |
Referenced by rf212_channel_clear(), rf212_init(), rf_get_channel(), and rf_set_channel().
#define RF212_REG_PHY_ED_LEVEL (0x07) |
Referenced by rf212_read().
#define RF212_REG_PHY_RSSI (0x06) |
#define RF212_REG_PHY_TX_PWR (0x05) |
#define RF212_REG_PHY_TX_TIME (0x3B) |
#define RF212_REG_PLL_CF (0x1A) |
#define RF212_REG_PLL_DCU (0x1B) |
#define RF212_REG_RX_CTRL (0x0A) |
#define RF212_REG_RX_SYN (0x15) |
#define RF212_REG_SFD_VALUE (0x0B) |
#define RF212_REG_SHORT_ADDR_0 (0x20) |
#define RF212_REG_SHORT_ADDR_1 (0x21) |
#define RF212_REG_TRX_CTRL_0 (0x03) |
#define RF212_REG_TRX_CTRL_1 (0x04) |
Referenced by rf212_init().
#define RF212_REG_TRX_CTRL_2 (0x0C) |
Referenced by rf212_init().
#define RF212_REG_TRX_RPC (0x16) |
#define RF212_REG_TRX_STATE (0x02) |
Referenced by rf212_init(), rf212_interrupt_poll(), rf212_transmit(), and rf_generate_random_seed().
#define RF212_REG_TRX_STATUS (0x01) |
Referenced by rf212_channel_clear(), and rf212_status().
#define RF212_REG_TST_AGC (0x3C) |
#define RF212_REG_TST_CTRL_DIGI (0x36) |
#define RF212_REG_TST_SDM (0x3D) |
#define RF212_REG_VERSION_NUM (0x1D) |
#define RF212_REG_VREG_CTRL (0x10) |
#define RF212_REG_XAH_CTRL_0 (0x2C) |
#define RF212_REG_XAH_CTRL_1 (0x17) |
#define RF212_REG_XAH_CTRL_2 (0x19) |
#define RF212_REG_XOSC_CTRL (0x12) |
#define RX_DISABLE (1) |
Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.
#define RX_ENABLE (0) |
Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.
#define RX_STATUS_CRC_OK (1 << 7) /* CRC/FCS */ |
#define RX_STATUS_TRAC_STATUS (0x70) |
#define SR_MAX_CSMA_RETRIES 0x2C, 0X0E, 1 |
#define SR_MAX_FRAME_RETRIES 0x2C, 0xF0, 4 |
#define SR_RND_VALUE 0x06, 0x60, 5 |
Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI.
#define SR_RX_PDT_DIS 0x15, 0x80, 7 |
Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN.
#define SRAM_ACCESS (0 << 5) |
#define STATE_BUSY_RX (0x01) |
Referenced by rf212_prepare(), rf212_receiving_packet(), rf212_transmit(), rf233_prepare(), rf233_receiving_packet(), and rf233_transmit().
#define STATE_BUSY_RX_AACK (0x11) |
Referenced by rf212_prepare(), rf212_receiving_packet(), rf212_transmit(), rf233_prepare(), rf233_receiving_packet(), and rf233_transmit().
#define STATE_BUSY_TX (0x02) /* 7.2 - 13.8 mA */ |
Referenced by rf212_prepare(), rf212_transmit(), rf233_prepare(), and rf233_transmit().
#define STATE_BUSY_TX_ARET (0x12) |
Referenced by rf212_prepare(), rf212_transmit(), rf233_prepare(), and rf233_transmit().
#define STATE_P_ON (0x00) |
Referenced by rf212_init(), and rf233_init().
#define STATE_PLL_ON (0x09) /* 5.2 mA */ |
Referenced by on(), rf212_transmit(), and rf233_transmit().
#define STATE_PREP_DEEP_SLEEP (0x10) |
#define STATE_RX_AACK_ON (0x16) |
Referenced by off().
#define STATE_RX_ON (0x06) /* 11.8 mA */ |
Referenced by off(), rf212_channel_clear(), and rf233_channel_clear().
#define STATE_SLEEP (0x0F) /* 0.2 uA */ |
#define STATE_TRANSITION (0x1F) |
#define STATE_TRX_OFF (0x08) /* 300 uA */ |
Referenced by on().
#define STATE_TX_ARET_ON (0x19) |
Referenced by on().
#define TRAC_CHANNEL_ACCESS_FAIL (3 << 5) |
#define TRAC_INVALID (7 << 5) |
Referenced by handle_tx_end_irq(), and tx_done_handling().
#define TRAC_NO_ACK (5 << 5) |
Referenced by handle_tx_end_irq(), and tx_done_handling().
#define TRAC_SUCCESS (0 << 5) |
Referenced by handle_tx_end_irq(), and tx_done_handling().
#define TRAC_SUCCESS_DATA_PENDING (1 << 5) |
Referenced by handle_tx_end_irq(), and tx_done_handling().
#define TRAC_SUCCESS_WAIT_FOR_ACK (2 << 5) |
#define TRX_BUFFER_LENGTH 128 /* bytes */ |
#define TRX_CCA_DONE (1 << 7) |
Referenced by rf212_channel_clear(), and rf233_channel_clear().
#define TRX_CCA_STATUS (1 << 6) |
Referenced by rf212_channel_clear(), and rf233_channel_clear().
#define TRX_CTRL_1_AUTO_CRC (1 << 5) |
#define TRX_CTRL_1_DIG2_TIMESTAMPING (1 << 6) /* pin DIG2 goes high ca 200us after SFD finished */ |
#define TRX_CTRL_1_DIG34_RXTX_INDICATOR TRX_CTRL_1_PA_EXT_EN /* synonym */ |
#define TRX_CTRL_1_FRAME_BUF_EMPTY_EN (1 << 4) /* IRQ pin turns into indicator during frame buffer reads */ |
#define TRX_CTRL_1_IRQ_MASK_MODE (1 << 1) /* irqs shown in IRQ_STATUS even if not in IRQ_MASK */ |
#define TRX_CTRL_1_IRQ_POL_ACTIVE_LOW (1 << 0) |
#define TRX_CTRL_1_PA_EXT_EN (1 << 7) /* pin DIG3/DIG4 indicates tx/rx mode */ |
#define TRX_CTRL_1_SPI_CMD_IRQ_STATUS (3 << 2) |
#define TRX_CTRL_1_SPI_CMD_RSSI (2 << 2) |
#define TRX_CTRL_1_SPI_CMD_TRX_STATUS (1 << 2) |
#define TRX_CTRL_2_RX_SAFE_MODE (1 << 7) /* disallow rx buffer overwrites */ |
#define TRX_STATE_TRAC_STATUS (0xE0) /* result of transaction in extended mode */ |
Referenced by rf212_interrupt_poll(), and rf233_interrupt_poll().
#define TRX_STATE_TRX_COMMAND (0x1F) |
#define TRX_STATUS (0x1F) /* radio status bit field */ |
#define TRXCMD_FORCE_PLL_ON (0x04) |
#define TRXCMD_FORCE_TRX_OFF (0x03) |
#define TRXCMD_NOP (0x00) |
#define TRXCMD_PLL_ON (0x09) |
Referenced by rf212_transmit(), rf233_transmit(), and rf_generate_random_seed().
#define TRXCMD_PREP_DEEP_SLEEP (0x10) |
#define TRXCMD_RX_AACK_ON (0x16) |
Referenced by on(), rf212_channel_clear(), rf212_interrupt_poll(), rf233_channel_clear(), and rf233_interrupt_poll().
#define TRXCMD_RX_ON (0x06) |
Referenced by on(), rf212_channel_clear(), rf212_transmit(), rf233_channel_clear(), rf233_transmit(), and rf_generate_random_seed().
#define TRXCMD_TRX_OFF (0x08) |
Referenced by off(), rf212_channel_clear(), rf212_init(), rf233_channel_clear(), rf233_init(), and rf_generate_random_seed().
#define TRXCMD_TX_ARET_ON (0x19) |
Referenced by rf212_transmit(), and rf233_transmit().
#define TRXCMD_TX_START (0x02) |
Referenced by rf212_transmit(), and rf233_transmit().
#define TXP_0 (0x07) |
#define TXP_1 (0x06) |
#define TXP_2 (0x05) |
#define TXP_2P5 (0x04) |
#define TXP_3 (0x03) |
#define TXP_3P4 (0x02) |
#define TXP_3P7 (0x01) |
#define TXP_4 (0x00) |
#define TXP_M1 (0x08) |
#define TXP_M12 (0x0E) |
#define TXP_M17 (0x0F) |
Referenced by rf212_set_txp(), and rf233_set_txp().
#define TXP_M2 (0x09) |
#define TXP_M3 (0x0A) |
#define TXP_M4 (0x0B) |
#define TXP_M6 (0x0C) |
#define TXP_M8 (0x0D) |
#define WRITE_ACCESS (1 << 6) |