 PHY component (DM9161A) | Driver for the dm9161a component |
| Ethernet Media Access Controller | See Quickstart guide for EMAC driver. |
| Universal Asynchronous Receiver Transceiver (UART) | The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions |
| Power Management Controller (PMC) | |
| Universal Synchronous Asynchronous | Receiver Transmitter (USART) |
 Standard I/O (stdio) | Common standard I/O driver that implements the stdio read and write functions on AVR and SAM devices |
  Standard serial I/O (stdio) | Common standard serial I/O management driver that implements a stdio serial interface on AVR and SAM devices |
| Peripheral Parallel Input/Output (PIO) Controller | |
| Ethernet Phy | This is the common API for Ethernet Phy on ARMs |
| Compiler abstraction layer and code utilities | Compiler abstraction layer and code utilities for AT91SAM |
| Preprocessor - Macro Repeat | |
| Preprocessor - Stringize | |
| Preprocessor - Token Paste | |
| Global interrupt management | This is a driver for global enabling and disabling of interrupts |
| Deprecated interrupt definitions | |
| Atmel part identification macros | This collection of macros identify which series and families that the various Atmel parts belong to |
| AVR UC3 parts | |
| AVR XMEGA parts | |
| megaAVR parts | |
| SAM parts | |
| Common IOPORT API | See Quick start guide for the common IOPORT service |
| Clock Management | |
| Generic Clock Management | Generic clocks are configurable clocks which run outside the system clock domain |
| Oscillator Management | This group contains functions and definitions related to configuring and enabling/disabling on-chip oscillators |
| PLL Management | This group contains functions and definitions related to configuring and enabling/disabling on-chip PLLs |
| System Clock Management | See Quick Start Guide for the System Clock Management service (SAM3A) |
| Power Manager (PM) | This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr service |
| Serial Interface (Serial) | See Quick start guide for Serial Interface service |
| Universal Synchronous Asynchronous Receiver | Transmitter (USART) |
| SAM3/4S/4L/4E/4N/4CM/4C/G Timer Counter (TC) Driver | This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's Timer Counter functionality |
| SAM3/4C/4CM/4CP/4E/4N/4S/G/V71/V70/S70/E70 Reset Controller (RSTC) Driver | This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's Reset Controller functionality |
| Generic board support | The generic board support module includes board-specific definitions and function prototypes, such as the board initialization function |
| General Purpose Input/Output | This is the common API for GPIO |
 Eth_phy_mii | |
 PHY registers Addresses | |
| Basic Mode Control Register (BMCR, 0) | List Bit definitions: MII_BMCR |
| Basic Mode Status Register (BMSR, 1) | Reserved bits: 6 to 0, Read as 0, ignore on write |
| PHY ID Identifier Register (PHYID, 2,3) | List definitions: MII_PHYID1, MII_PHYID2 |
| Auto-negotiation (ANAR, 4; ANLPAR, 5) | |
| Auto-negotiation Expansion Register (ANER, 6) | List Bit definitions: MII_ANER |
| Specified Configuration Register (DSCR, 16) | List Bit definitions: MII_DSCR |
| Specified Configuration and Status Register (DSCSR, 17) | List Bit definitions: MII_DSCSR |
| 10BASE-T Configuration/Status (10BTCSR, 18) | List Bit definitions: MII_10BTCSR |
| Specified Interrupt Register (MDINTR, 21) | List Bit definitions: MII_MDINTR |
1.8.5