#include "tal_types.h"Macros | |
| #define | ACK_DISABLE (1) |
| Constant ACK_DISABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1. More... | |
| #define | ACK_ENABLE (0) |
| Constant ACK_ENABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1. More... | |
| #define | ACK_TIME_12_SYMBOLS (0) |
| Constant ACK_TIME_12_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1. More... | |
| #define | ACK_TIME_2_SYMBOLS (1) |
| Constant ACK_TIME_2_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1. More... | |
| #define | AES_BASE_ADDR (0x80) |
| Register addresses. More... | |
| #define | AES_DIR_DECRYPT (1) |
| Constant AES_DIR_DECRYPT for sub-register SR_AES_DIR in register AES_CTRL. More... | |
| #define | AES_DIR_ENCRYPT (0) |
| Constant AES_DIR_ENCRYPT for sub-register SR_AES_DIR in register AES_CTRL. More... | |
| #define | AES_DONE (1) |
| Constant AES_DONE for sub-register SR_AES_DONE in register AES_STATUS. More... | |
| #define | AES_ERROR (1) |
| Constant AES_ERROR for sub-register SR_AES_ER in register AES_STATUS. More... | |
| #define | AES_MODE_CBC (2) |
| Constant AES_MODE_CBC for sub-register SR_AES_MODE in register AES_CTRL. More... | |
| #define | AES_MODE_ECB (0) |
| Constant AES_MODE_ECB for sub-register SR_AES_MODE in register AES_CTRL. More... | |
| #define | AES_MODE_KEY (1) |
| Constant AES_MODE_KEY for sub-register SR_AES_MODE in register AES_CTRL. More... | |
| #define | AES_NO_ERROR (0) |
| Constant AES_NO_ERROR for sub-register SR_AES_ER in register AES_STATUS. More... | |
| #define | AES_NOT_DONE (0) |
| Constant AES_NOT_DONE for sub-register SR_AES_DONE in register AES_STATUS. More... | |
| #define | AES_REQUEST (1) |
| Constant AES_REQUEST for sub-register SR_AES_REQUEST in register AES_CTRL. More... | |
| #define | ALT_SPECTRUM_DISABLE (0) |
| Constant ALT_SPECTRUM_DISABLE for sub-register SR_ALT_SPECTRUM in register TRX_CTRL_2. More... | |
| #define | ALT_SPECTRUM_ENABLE (1) |
| Constant ALT_SPECTRUM_ENABLE for sub-register SR_ALT_SPECTRUM in register TRX_CTRL_2. More... | |
| #define | ALTRATE_100_KBPS_OR_250_KBPS (0) |
| Constant ALTRATE_100_KBPS_OR_250_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More... | |
| #define | ALTRATE_200_KBPS_OR_500_KBPS (1) |
| Constant ALTRATE_200_KBPS_OR_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More... | |
| #define | ALTRATE_400_KBPS_OR_1_MBPS (2) |
| Constant ALTRATE_400_KBPS_OR_1_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More... | |
| #define | ANT_CTRL_1 (1) |
| Constant ANT_CTRL_1 for sub-register SR_ANT_CTRL in register ANT_DIV. More... | |
| #define | ANT_CTRL_2 (2) |
| Constant ANT_CTRL_2 for sub-register SR_ANT_CTRL in register ANT_DIV. More... | |
| #define | ANT_DIV_DISABLE (0) |
| Constant ANT_DIV_DISABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV. More... | |
| #define | ANT_DIV_ENABLE (1) |
| Constant ANT_DIV_ENABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV. More... | |
| #define | ANT_EXT_SW_DISABLE (0) |
| Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV. More... | |
| #define | ANT_EXT_SW_ENABLE (1) |
| Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV. More... | |
| #define | ANT_SEL_ANTENNA_0 (0) |
| Constant ANT_SEL_ANTENNA_0 for sub-register SR_ANT_SEL in register ANT_DIV. More... | |
| #define | ANT_SEL_ANTENNA_1 (1) |
| Constant ANT_SEL_ANTENNA_1 for sub-register SR_ANT_SEL in register ANT_DIV. More... | |
| #define | BATMON_HR_HIGH (1) |
| Constant BATMON_HR_HIGH for sub-register SR_BATMON_HR in register BATMON. More... | |
| #define | BATMON_HR_LOW (0) |
| Constant BATMON_HR_LOW for sub-register SR_BATMON_HR in register BATMON. More... | |
| #define | BATMON_NOT_VALID (0) |
| Constant BATMON_NOT_VALID for sub-register SR_BATMON_OK in register BATMON. More... | |
| #define | BATMON_VALID (1) |
| Constant BATMON_VALID for sub-register SR_BATMON_OK in register BATMON. More... | |
| #define | BPSK_MODE (0) |
| Constant BPSK_MODE for sub-register SR_BPSK_OQPSK in register TRX_CTRL_2. More... | |
| #define | BPSK_TX_OFFSET (3) |
| #define | CCA_CH_BUSY (0) |
| Constant CCA_CH_BUSY for sub-register SR_CCA_STATUS in register TRX_STATUS. More... | |
| #define | CCA_CH_IDLE (1) |
| Constant CCA_CH_IDLE for sub-register SR_CCA_STATUS in register TRX_STATUS. More... | |
| #define | CCA_COMPLETED (1) |
| Constant CCA_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS. More... | |
| #define | CCA_CS_THRES_15 (0xF) |
| Constant CCA_CS_THRES_15 for sub-register SR_CCA_CS_THRES in register CCA_THRES. More... | |
| #define | CCA_CS_THRES_7 (0x7) |
| Constant CCA_CS_THRES_7 for sub-register SR_CCA_CS_THRES in register CCA_THRES. More... | |
| #define | CCA_DETECTION_TIME_SYMBOL (8) |
| #define | CCA_DURATION_SYM |
| #define | CCA_MODE_0 (0) |
| Constant CCA_MODE_0 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More... | |
| #define | CCA_MODE_1 (1) |
| Constant CCA_MODE_1 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More... | |
| #define | CCA_MODE_2 (2) |
| Constant CCA_MODE_2 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More... | |
| #define | CCA_MODE_3 (3) |
| Constant CCA_MODE_3 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More... | |
| #define | CCA_NO_START (0) |
| Constant CCA_NO_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA. More... | |
| #define | CCA_ONGOING (0) |
| Constant CCA_ONGOING for sub-register SR_CCA_DONE in register TRX_STATUS. More... | |
| #define | CCA_PRE_START_DURATION_US (20) |
| #define | CCA_PREPARATION_DURATION_US (50) |
| #define | CCA_PROCESS_TIME_SYM (1) |
| #define | CCA_PROCESS_TIME_US (12) |
| #define | CCA_START (1) |
| Constant CCA_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA. More... | |
| #define | CLEAR_PD (0) |
| Constant CLEAR_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1. More... | |
| #define | CLKM_16MHZ (5) |
| Constant CLKM_16MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CLKM_1_4MHZ (6) |
| Constant CLKM_1_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CLKM_1MHZ (1) |
| Constant CLKM_1MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CLKM_2MHZ (2) |
| Constant CLKM_2MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CLKM_4MHZ (3) |
| Constant CLKM_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CLKM_8MHZ (4) |
| Constant CLKM_8MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CLKM_NO_CLOCK (0) |
| Constant CLKM_NO_CLOCK for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CLKM_SHA_DISABLE (0) |
| Constant CLKM_SHA_DISABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0. More... | |
| #define | CLKM_SHA_ENABLE (1) |
| Constant CLKM_SHA_ENABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0. More... | |
| #define | CLKM_SYMBOL_RATE (7) |
| Constant CLKM_SYMBOL_RATE for sub-register SR_CLKM_CTRL in register TRX_CTRL_0. More... | |
| #define | CRC16_NOT_VALID (0) |
| Constant CRC16_NOT_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI. More... | |
| #define | CRC16_VALID (1) |
| Constant CRC16_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI. More... | |
| #define | CSMA_MODE_ENABLE (0) |
| Constant CSMA_MODE_ENABLE for sub-register SR_CSMA_LBT_MODE in register XAH_CTRL_1. More... | |
| #define | EXT_FRONTEND_DISABLE (0) |
| Constant EXT_FRONTEND_DISABLE for sub-register SR_PA_EXT_EN in register TRX_CTRL_1. More... | |
| #define | EXT_FRONTEND_ENABLE (1) |
| Constant EXT_FRONTEND_ENABLE for sub-register SR_PA_EXT_EN in register TRX_CTRL_1. More... | |
| #define | FLTR_RES_FT_DISABLE (0) |
| Constant FLTR_RES_FT_DISABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1. More... | |
| #define | FLTR_RES_FT_ENABLE (1) |
| Constant FLTR_RES_FT_ENABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1. More... | |
| #define | FRAME_VERSION_00 (0) |
| Constant FRAME_VERSION_00 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More... | |
| #define | FRAME_VERSION_01 (1) |
| Constant FRAME_VERSION_01 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More... | |
| #define | FRAME_VERSION_012 (2) |
| Constant FRAME_VERSION_012 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More... | |
| #define | FRAME_VERSION_IGNORED (3) |
| Constant FRAME_VERSION_IGNORED for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More... | |
| #define | HIGH_DATA_RATE (1) |
| Constant HIGH_DATA_RATE for sub-register SR_SUB_MODE in register TRX_CTRL_2. More... | |
| #define | I_AM_COORD_DISABLE (0) |
| Constant I_AM_COORD_DISABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1. More... | |
| #define | I_AM_COORD_ENABLE (1) |
| Constant I_AM_COORD_ENABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1. More... | |
| #define | IEEE_CHANNEL_0 (0x00) |
| Constant IEEE_CHANNEL_0 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_1 (0x01) |
| Constant IEEE_CHANNEL_1 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_10 (0x0A) |
| Constant IEEE_CHANNEL_10 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_2 (0x02) |
| Constant IEEE_CHANNEL_2 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_3 (0x03) |
| Constant IEEE_CHANNEL_3 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_4 (0x04) |
| Constant IEEE_CHANNEL_4 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_5 (0x05) |
| Constant IEEE_CHANNEL_5 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_6 (0x06) |
| Constant IEEE_CHANNEL_6 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_7 (0x07) |
| Constant IEEE_CHANNEL_7 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_8 (0x08) |
| Constant IEEE_CHANNEL_8 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IEEE_CHANNEL_9 (0x09) |
| Constant IEEE_CHANNEL_9 for sub-register SR_CHANNEL in register PHY_CC_CCA. More... | |
| #define | IF_SHIFT_MODE_AUTO (1) |
| Constant IF_SHIFT_MODE_AUTO for sub-register SR_IF_SHIFT_MODE in register RF_CTRL_0. More... | |
| #define | IF_SHIFT_MODE_OFF (0) |
| Constant IF_SHIFT_MODE_OFF for sub-register SR_IF_SHIFT_MODE in register RF_CTRL_0. More... | |
| #define | IRQ_HIGH_ACTIVE (0) |
| Constant IRQ_HIGH_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1. More... | |
| #define | IRQ_LOW_ACTIVE (1) |
| Constant IRQ_LOW_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1. More... | |
| #define | IRQ_MASK_MODE_OFF (0) |
| Constant IRQ_MASK_MODE_OFF for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1. More... | |
| #define | IRQ_MASK_MODE_ON (1) |
| Constant IRQ_MASK_MODE_ON for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1. More... | |
| #define | JCM_DISABLE (0) |
| Constant JCM_DISABLE for sub-register SR_JCM_EN in register RX_CTRL. More... | |
| #define | JCM_ENABLE (1) |
| Constant JCM_ENABLE for sub-register SR_JCM_EN in register RX_CTRL. More... | |
| #define | LBT_MODE_ENABLE (1) |
| Constant LBT_MODE_ENABLE for sub-register SR_CSMA_LBT_MODE in register XAH_CTRL_1. More... | |
| #define | LOW_DATA_RATE (0) |
| Constant LOW_DATA_RATE for sub-register SR_SUB_MODE in register TRX_CTRL_2. More... | |
| #define | NEWRATE_500_KBPS (3) |
| Constant NEWRATE_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More... | |
| #define | OQPSK_MODE (1) |
| Constant OQPSK_MODE for sub-register SR_BPSK_OQPSK in register TRX_CTRL_2. More... | |
| #define | OQPSK_SCRAM_DISABLE (0) |
| Constant OQPSK_SCRAM_DISABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2. More... | |
| #define | OQPSK_SCRAM_ENABLE (1) |
| Constant OQPSK_SCRAM_ENABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2. More... | |
| #define | OQPSK_TX_OFFSET (2) |
| Constant OQPSK_TX_OFFSET for sub-register SR_GC_TX_OFFS in register RF_CTRL_0. More... | |
| #define | P_ON_TO_CLKM_AVAILABLE_MAX_US (1000) |
| #define | P_ON_TO_CLKM_AVAILABLE_TYP_US (420) |
| #define | PA_BOOST_DISABLE (0) |
| Constant PA_BOOST_DISABLE for sub-register SR_PA_BOOST in register PHY_TX_PWR. More... | |
| #define | PA_BOOST_ENABLE (1) |
| Constant PA_BOOST_ENABLE for sub-register SR_PA_BOOST in register PHY_TX_PWR. More... | |
| #define | PAD_CLKM_2_MA (0) |
| Constant PAD_CLKM_2_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0. More... | |
| #define | PAD_CLKM_4_MA (1) |
| Constant PAD_CLKM_4_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0. More... | |
| #define | PAD_CLKM_6_MA (2) |
| Constant PAD_CLKM_6_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0. More... | |
| #define | PAD_CLKM_8_MA (3) |
| Constant PAD_CLKM_8_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0. More... | |
| #define | PAD_IO_2_MA (0) |
| Constant PAD_IO_2_MA for sub-register SR_PAD_IO in register TRX_CTRL_0. More... | |
| #define | PAD_IO_4_MA (1) |
| Constant PAD_IO_4_MA for sub-register SR_PAD_IO in register TRX_CTRL_0. More... | |
| #define | PAD_IO_6_MA (2) |
| Constant PAD_IO_6_MA for sub-register SR_PAD_IO in register TRX_CTRL_0. More... | |
| #define | PAD_IO_8_MA (3) |
| Constant PAD_IO_8_MA for sub-register SR_PAD_IO in register TRX_CTRL_0. More... | |
| #define | PART_NUM_AT86RF212B (0x07) |
| Constant PART_NUM_AT86RF212B for sub-register SR_PART_NUM in register PART_NUM. More... | |
| #define | PRE_TX_DURATION_US (32) |
| #define | PROM_MODE_DISABLE (0) |
| Constant PROM_MODE_DISABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1. More... | |
| #define | PROM_MODE_ENABLE (1) |
| Constant PROM_MODE_ENABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1. More... | |
| #define | RG_AES_CTRL (0x03) |
| Offset for register AES_CTRL. More... | |
| #define | RG_AES_CTRL_MIRROR (0x14) |
| Offset for register AES_CTRL_MIRROR. More... | |
| #define | RG_AES_STATE_KEY_0 (0x04) |
| Offset for register AES_STATE_KEY_0. More... | |
| #define | RG_AES_STATUS (0x02) |
| Offset for register AES_STATUS. More... | |
| #define | RG_ANT_DIV (0x0D) |
| Offset for register ANT_DIV. More... | |
| #define | RG_BATMON (0x11) |
| Offset for register BATMON. More... | |
| #define | RG_CC_CTRL_0 (0x13) |
| Offset for register CC_CTRL_0. More... | |
| #define | RG_CC_CTRL_1 (0x14) |
| Offset for register CC_CTRL_1. More... | |
| #define | RG_CCA_THRES (0x09) |
| Offset for register CCA_THRES. More... | |
| #define | RG_CSMA_BE (0x2F) |
| Offset for register CSMA_BE. More... | |
| #define | RG_CSMA_SEED_0 (0x2D) |
| Offset for register CSMA_SEED_0. More... | |
| #define | RG_CSMA_SEED_1 (0x2E) |
| Offset for register CSMA_SEED_1. More... | |
| #define | RG_ED (0x01) |
| Offset for register ED. More... | |
| #define | RG_FTN_CTRL (0x18) |
| Offset for register FTN_CTRL. More... | |
| #define | RG_IEEE_ADDR_0 (0x24) |
| Offset for register IEEE_ADDR_0. More... | |
| #define | RG_IEEE_ADDR_1 (0x25) |
| Offset for register IEEE_ADDR_1. More... | |
| #define | RG_IEEE_ADDR_2 (0x26) |
| Offset for register IEEE_ADDR_2. More... | |
| #define | RG_IEEE_ADDR_3 (0x27) |
| Offset for register IEEE_ADDR_3. More... | |
| #define | RG_IEEE_ADDR_4 (0x28) |
| Offset for register IEEE_ADDR_4. More... | |
| #define | RG_IEEE_ADDR_5 (0x29) |
| Offset for register IEEE_ADDR_5. More... | |
| #define | RG_IEEE_ADDR_6 (0x2A) |
| Offset for register IEEE_ADDR_6. More... | |
| #define | RG_IEEE_ADDR_7 (0x2B) |
| Offset for register IEEE_ADDR_7. More... | |
| #define | RG_IRQ_MASK (0x0E) |
| Offset for register IRQ_MASK. More... | |
| #define | RG_IRQ_STATUS (0x0F) |
| Offset for register IRQ_STATUS. More... | |
| #define | RG_LQI (0x00) |
| Offset for register LQI. More... | |
| #define | RG_MAN_ID_0 (0x1E) |
| Offset for register MAN_ID_0. More... | |
| #define | RG_MAN_ID_1 (0x1F) |
| Offset for register MAN_ID_1. More... | |
| #define | RG_PAN_ID_0 (0x22) |
| Offset for register PAN_ID_0. More... | |
| #define | RG_PAN_ID_1 (0x23) |
| Offset for register PAN_ID_1. More... | |
| #define | RG_PART_NUM (0x1C) |
| Offset for register PART_NUM. More... | |
| #define | RG_PHY_CC_CCA (0x08) |
| Offset for register PHY_CC_CCA. More... | |
| #define | RG_PHY_ED_LEVEL (0x07) |
| Offset for register PHY_ED_LEVEL. More... | |
| #define | RG_PHY_RSSI (0x06) |
| Offset for register PHY_RSSI. More... | |
| #define | RG_PHY_TX_PWR (0x05) |
| Offset for register PHY_TX_PWR. More... | |
| #define | RG_PLL_CF (0x1A) |
| Offset for register PLL_CF. More... | |
| #define | RG_PLL_DCU (0x1B) |
| Offset for register PLL_DCU. More... | |
| #define | RG_RF_CTRL_0 (0x16) |
| Offset for register RF_CTRL_0. More... | |
| #define | RG_RX_CTRL (0x0A) |
| Offset for register RX_CTRL. More... | |
| #define | RG_RX_STATUS (0x02) |
| Offset for register RX_STATUS. More... | |
| #define | RG_RX_SYN (0x15) |
| Offset for register RX_SYN. More... | |
| #define | RG_SFD_VALUE (0x0B) |
| Offset for register SFD_VALUE. More... | |
| #define | RG_SHORT_ADDR_0 (0x20) |
| Offset for register SHORT_ADDR_0. More... | |
| #define | RG_SHORT_ADDR_1 (0x21) |
| Offset for register SHORT_ADDR_1. More... | |
| #define | RG_TRX_CTRL_0 (0x03) |
| Offset for register TRX_CTRL_0. More... | |
| #define | RG_TRX_CTRL_1 (0x04) |
| Offset for register TRX_CTRL_1. More... | |
| #define | RG_TRX_CTRL_2 (0x0C) |
| Offset for register TRX_CTRL_2. More... | |
| #define | RG_TRX_STATE (0x02) |
| Offset for register TRX_STATE. More... | |
| #define | RG_TRX_STATUS (0x01) |
| Offset for register TRX_STATUS. More... | |
| #define | RG_VERSION_NUM (0x1D) |
| Offset for register VERSION_NUM. More... | |
| #define | RG_VREG_CTRL (0x10) |
| Offset for register VREG_CTRL. More... | |
| #define | RG_XAH_CTRL_0 (0x2C) |
| Offset for register XAH_CTRL_0. More... | |
| #define | RG_XAH_CTRL_1 (0x17) |
| Offset for register XAH_CTRL_1. More... | |
| #define | RG_XOSC_CTRL (0x12) |
| Offset for register XOSC_CTRL. More... | |
| #define | RSSI_BASE_VAL_BPSK_300_DBM (-100) |
| #define | RSSI_BASE_VAL_BPSK_600_DBM (-99) |
| #define | RSSI_BASE_VAL_OQPSK_1000_RC_DBM (-98) |
| #define | RSSI_BASE_VAL_OQPSK_1000_SIN_DBM (-99) |
| #define | RSSI_BASE_VAL_OQPSK_400_RC_DBM (-98) |
| #define | RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM (-98) |
| #define | RST_PULSE_WIDTH_NS (625) |
| Typical timing values. More... | |
| #define | RST_PULSE_WIDTH_US |
| #define | RX_BL_CTRL_DISABLE (0) |
| Constant RX_BL_CTRL_DISABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1. More... | |
| #define | RX_BL_CTRL_ENABLE (1) |
| Constant RX_BL_CTRL_ENABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1. More... | |
| #define | RX_DISABLE (1) |
| Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More... | |
| #define | RX_ENABLE (0) |
| Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More... | |
| #define | RX_SAFE_MODE_DISABLE (0) |
| Constant RX_SAFE_MODE_DISABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2. More... | |
| #define | RX_SAFE_MODE_ENABLE (1) |
| Constant RX_SAFE_MODE_ENABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2. More... | |
| #define | RX_TIMESTAMPING_DISABLE (0) |
| Constant RX_TIMESTAMPING_DISABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1. More... | |
| #define | RX_TIMESTAMPING_ENABLE (1) |
| Constant RX_TIMESTAMPING_ENABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1. More... | |
| #define | RXAPPENDIX_BASE_ADDR (0x00) |
| Base address and size for RX frame appendix. More... | |
| #define | RXAPPENDIX_SIZE (3) |
| #define | RXO_DISABLE (0) |
| Constant RXO_DISABLE for sub-register SR_RX_OVERRIDE in register RX_SYN. More... | |
| #define | RXO_ENABLE (6) |
| Constant RXO_ENABLE for sub-register SR_RX_OVERRIDE in register RX_SYN. More... | |
| #define | SET_PD (1) |
| Constant SET_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1. More... | |
| #define | SLEEP_TO_TRX_OFF_MAX_US (1000) |
| #define | SLEEP_TO_TRX_OFF_TYP_US (420) |
| #define | SPI_CMD_MODE_DEFAULT (0) |
| Constant SPI_CMD_MODE_DEFAULT for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More... | |
| #define | SPI_CMD_MODE_IRQ_STATUS (3) |
| Constant SPI_CMD_MODE_IRQ_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More... | |
| #define | SPI_CMD_MODE_PHY_RSSI (2) |
| Constant SPI_CMD_MODE_PHY_RSSI for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More... | |
| #define | SPI_CMD_MODE_TRX_STATUS (1) |
| Constant SPI_CMD_MODE_TRX_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1. More... | |
| #define | SR_AACK_ACK_TIME 0x17, 0x04, 2 |
| Access parameters for sub-register AACK_ACK_TIME in register RG_XAH_CTRL_1. More... | |
| #define | SR_AACK_DIS_ACK 0x2E, 0x10, 4 |
| Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1. More... | |
| #define | SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 |
| Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1. More... | |
| #define | SR_AACK_FVN_MODE 0x2E, 0xC0, 6 |
| Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More... | |
| #define | SR_AACK_I_AM_COORD 0x2E, 0x08, 3 |
| Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1. More... | |
| #define | SR_AACK_PROM_MODE 0x17, 0x02, 1 |
| Sub-registers of Register RG_XAH_CTRL_1. More... | |
| #define | SR_AACK_SET_PD 0x2E, 0x20, 5 |
| Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More... | |
| #define | SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 |
| Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1. More... | |
| #define | SR_AES_DIR 0x03, 0x08, 3 |
| Sub-registers of Register RG_AES_CTRL. More... | |
| #define | SR_AES_DONE 0x02, 0x01, 0 |
| Sub-registers of Register RG_AES_STATUS. More... | |
| #define | SR_AES_ER 0x02, 0x80, 7 |
| Access parameters for sub-register AES_ER in register RG_AES_STATUS. More... | |
| #define | SR_AES_MODE 0x03, 0x70, 4 |
| Access parameters for sub-register AES_MODE in register RG_AES_CTRL. More... | |
| #define | SR_AES_REQUEST 0x03, 0x80, 7 |
| Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL. More... | |
| #define | SR_ALT_SPECTRUM 0x0C, 0x10, 4 |
| Access parameters for sub-register ALT_SPECTRUM in register RG_TRX_CTRL_2. More... | |
| #define | SR_ANT_CTRL 0x0D, 0x03, 0 |
| Sub-registers of Register RG_ANT_DIV. More... | |
| #define | SR_ANT_DIV_EN 0x0D, 0x08, 3 |
| Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV. More... | |
| #define | SR_ANT_EXT_SW_EN 0x0D, 0x04, 2 |
| Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV. More... | |
| #define | SR_ANT_SEL 0x0D, 0x80, 7 |
| Access parameters for sub-register ANT_SEL in register RG_ANT_DIV. More... | |
| #define | SR_AVDD_OK 0x10, 0x40, 6 |
| Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL. More... | |
| #define | SR_AVREG_EXT 0x10, 0x80, 7 |
| Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL. More... | |
| #define | SR_BATMON_HR 0x11, 0x10, 4 |
| Access parameters for sub-register BATMON_HR in register RG_BATMON. More... | |
| #define | SR_BATMON_OK 0x11, 0x20, 5 |
| Access parameters for sub-register BATMON_OK in register RG_BATMON. More... | |
| #define | SR_BATMON_VTH 0x11, 0x0F, 0 |
| Sub-registers of Register RG_BATMON. More... | |
| #define | SR_BPSK_OQPSK 0x0C, 0x08, 3 |
| Access parameters for sub-register BPSK_OQPSK in register RG_TRX_CTRL_2. More... | |
| #define | SR_CC_BAND 0x14, 0x07, 0 |
| Sub-registers of Register RG_CC_CTRL_1. More... | |
| #define | SR_CC_NUMBER 0x13, 0xFF, 0 |
| Sub-registers of Register RG_CC_CTRL_0. More... | |
| #define | SR_CCA_CS_THRES 0x09, 0xF0, 4 |
| Access parameters for sub-register CCA_CS_THRES in register RG_CCA_THRES. More... | |
| #define | SR_CCA_DONE 0x01, 0x80, 7 |
| Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS. More... | |
| #define | SR_CCA_ED_THRES 0x09, 0x0F, 0 |
| Sub-registers of Register RG_CCA_THRES. More... | |
| #define | SR_CCA_MODE 0x08, 0x60, 5 |
| Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA. More... | |
| #define | SR_CCA_REQUEST 0x08, 0x80, 7 |
| Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA. More... | |
| #define | SR_CCA_STATUS 0x01, 0x40, 6 |
| Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS. More... | |
| #define | SR_CHANNEL 0x08, 0x1F, 0 |
| Sub-registers of Register RG_PHY_CC_CCA. More... | |
| #define | SR_CLKM_CTRL 0x03, 0x07, 0 |
| Sub-registers of Register RG_TRX_CTRL_0. More... | |
| #define | SR_CLKM_SHA_SEL 0x03, 0x08, 3 |
| Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0. More... | |
| #define | SR_CSMA_LBT_MODE 0x17, 0x40, 6 |
| Access parameters for sub-register CSMA_LBT_MODE in register RG_XAH_CTRL_1. More... | |
| #define | SR_CSMA_SEED_0 0x2D, 0xFF, 0 |
| Sub-registers of Register RG_CSMA_SEED_0. More... | |
| #define | SR_CSMA_SEED_1 0x2E, 0x07, 0 |
| Sub-registers of Register RG_CSMA_SEED_1. More... | |
| #define | SR_DVDD_OK 0x10, 0x04, 2 |
| Sub-registers of Register RG_VREG_CTRL. More... | |
| #define | SR_DVREG_EXT 0x10, 0x08, 3 |
| Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL. More... | |
| #define | SR_ED_APX 0x01, 0xFF, 0 |
| Sub-registers of Register RG_ED. More... | |
| #define | SR_ED_LEVEL 0x07, 0xFF, 0 |
| Sub-registers of Register RG_PHY_ED_LEVEL. More... | |
| #define | SR_FTN_START 0x18, 0x80, 7 |
| Sub-registers of Register RG_FTN_CTRL. More... | |
| #define | SR_GC_PA 0x05, 0x60, 5 |
| Access parameters for sub-register GC_PA in register RG_PHY_TX_PWR. More... | |
| #define | SR_GC_TX_OFFS 0x16, 0x03, 0 |
| Sub-registers of Register RG_RF_CTRL_0. More... | |
| #define | SR_IEEE_ADDR_0 0x24, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_0. More... | |
| #define | SR_IEEE_ADDR_1 0x25, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_1. More... | |
| #define | SR_IEEE_ADDR_2 0x26, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_2. More... | |
| #define | SR_IEEE_ADDR_3 0x27, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_3. More... | |
| #define | SR_IEEE_ADDR_4 0x28, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_4. More... | |
| #define | SR_IEEE_ADDR_5 0x29, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_5. More... | |
| #define | SR_IEEE_ADDR_6 0x2A, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_6. More... | |
| #define | SR_IEEE_ADDR_7 0x2B, 0xFF, 0 |
| Sub-registers of Register RG_IEEE_ADDR_7. More... | |
| #define | SR_IF_SHIFT_MODE 0x16, 0x0C, 2 |
| Access parameters for sub-register IF_SHIFT_MODE in register RG_RF_CTRL_0. More... | |
| #define | SR_IRQ_0_PLL_LOCK 0x0F, 0x01, 0 |
| Sub-registers of Register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_1_PLL_UNLOCK 0x0F, 0x02, 1 |
| Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_2_EXT_EN 0x04, 0x40, 6 |
| Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1. More... | |
| #define | SR_IRQ_2_RX_START 0x0F, 0x04, 2 |
| Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_3_TRX_END 0x0F, 0x08, 3 |
| Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_4_CCA_ED_DONE 0x0F, 0x10, 4 |
| Access parameters for sub-register IRQ_4_CCA_ED_DONE in register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_5_AMI 0x0F, 0x20, 5 |
| Access parameters for sub-register IRQ_5_AMI in register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_6_TRX_UR 0x0F, 0x40, 6 |
| Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_7_BAT_LOW 0x0F, 0x80, 7 |
| Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS. More... | |
| #define | SR_IRQ_MASK 0x0E, 0xFF, 0 |
| Sub-registers of Register RG_IRQ_MASK. More... | |
| #define | SR_IRQ_MASK_MODE 0x04, 0x02, 1 |
| Access parameters for sub-register IRQ_MASK_MODE in register RG_TRX_CTRL_1. More... | |
| #define | SR_IRQ_POLARITY 0x04, 0x01, 0 |
| Sub-registers of Register RG_TRX_CTRL_1. More... | |
| #define | SR_JCM_EN 0x0A, 0x20, 5 |
| Sub-registers of Register RG_RX_CTRL. More... | |
| #define | SR_LQI_APX 0x00, 0xFF, 0 |
| Sub-registers of Register RG_LQI. More... | |
| #define | SR_MAN_ID_0 0x1E, 0xFF, 0 |
| Sub-registers of Register RG_MAN_ID_0. More... | |
| #define | SR_MAN_ID_1 0x1F, 0xFF, 0 |
| Sub-registers of Register RG_MAN_ID_1. More... | |
| #define | SR_MAX_BE 0x2F, 0xF0, 4 |
| Access parameters for sub-register MAX_BE in register RG_CSMA_BE. More... | |
| #define | SR_MAX_CSMA_RETRIES 0x2C, 0x0E, 1 |
| Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0. More... | |
| #define | SR_MAX_FRAME_RETRIES 0x2C, 0xF0, 4 |
| Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0. More... | |
| #define | SR_MIN_BE 0x2F, 0x0F, 0 |
| Sub-registers of Register RG_CSMA_BE. More... | |
| #define | SR_OQPSK_DATA_RATE 0x0C, 0x03, 0 |
| Sub-registers of Register RG_TRX_CTRL_2. More... | |
| #define | SR_OQPSK_SCRAM_EN 0x0C, 0x20, 5 |
| Access parameters for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2. More... | |
| #define | SR_PA_BOOST 0x05, 0x80, 7 |
| Access parameters for sub-register PA_BOOST in register RG_PHY_TX_PWR. More... | |
| #define | SR_PA_EXT_EN 0x04, 0x80, 7 |
| Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1. More... | |
| #define | SR_PA_LT 0x16, 0xC0, 6 |
| Access parameters for sub-register PA_LT in register RG_RF_CTRL_0. More... | |
| #define | SR_PAD_IO 0x03, 0xC0, 6 |
| Access parameters for sub-register PAD_IO in register RG_TRX_CTRL_0. More... | |
| #define | SR_PAD_IO_CLKM 0x03, 0x30, 4 |
| Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0. More... | |
| #define | SR_PAN_ID_0 0x22, 0xFF, 0 |
| Sub-registers of Register RG_PAN_ID_0. More... | |
| #define | SR_PAN_ID_1 0x23, 0xFF, 0 |
| Sub-registers of Register RG_PAN_ID_1. More... | |
| #define | SR_PART_NUM 0x1C, 0xFF, 0 |
| Sub-registers of Register RG_PART_NUM. More... | |
| #define | SR_PLL_CF_START 0x1A, 0x80, 7 |
| Sub-registers of Register RG_PLL_CF. More... | |
| #define | SR_PLL_DCU_START 0x1B, 0x80, 7 |
| Sub-registers of Register RG_PLL_DCU. More... | |
| #define | SR_PLL_LOCK_CP 0x11, 0x80, 7 |
| Access parameters for sub-register PLL_LOCK_CP in register RG_BATMON. More... | |
| #define | SR_RND_VALUE 0x06, 0x60, 5 |
| Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI. More... | |
| #define | SR_RSSI 0x06, 0x1F, 0 |
| Sub-registers of Register RG_PHY_RSSI. More... | |
| #define | SR_RX_BL_CTRL 0x04, 0x10, 4 |
| Access parameters for sub-register RX_BL_CTRL in register RG_TRX_CTRL_1. More... | |
| #define | SR_RX_CRC_VALID 0x06, 0x80, 7 |
| Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI. More... | |
| #define | SR_RX_CRC_VALID_APX 0x02, 0x80, 7 |
| Access parameters for sub-register RX_CRC_VALID_APX in register RG_RX_STATUS. More... | |
| #define | SR_RX_OVERRIDE 0x15, 0x70, 4 |
| Access parameters for sub-register RX_OVERRIDE in register RG_RX_SYN. More... | |
| #define | SR_RX_PDT_DIS 0x15, 0x80, 7 |
| Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN. More... | |
| #define | SR_RX_PDT_LEVEL 0x15, 0x0F, 0 |
| Sub-registers of Register RG_RX_SYN. More... | |
| #define | SR_RX_SAFE_MODE 0x0C, 0x80, 7 |
| Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2. More... | |
| #define | SR_SFD_VALUE 0x0B, 0xFF, 0 |
| Sub-registers of Register RG_SFD_VALUE. More... | |
| #define | SR_SHORT_ADDR_0 0x20, 0xFF, 0 |
| Sub-registers of Register RG_SHORT_ADDR_0. More... | |
| #define | SR_SHORT_ADDR_1 0x21, 0xFF, 0 |
| Sub-registers of Register RG_SHORT_ADDR_1. More... | |
| #define | SR_SLOTTED_OPERATION 0x2C, 0x01, 0 |
| Sub-registers of Register RG_XAH_CTRL_0. More... | |
| #define | SR_SPI_CMD_MODE 0x04, 0x0C, 2 |
| Access parameters for sub-register SPI_CMD_MODE in register RG_TRX_CTRL_1. More... | |
| #define | SR_SUB_MODE 0x0C, 0x04, 2 |
| Access parameters for sub-register SUB_MODE in register RG_TRX_CTRL_2. More... | |
| #define | SR_TRAC_STATUS 0x02, 0xE0, 5 |
| Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE. More... | |
| #define | SR_TRAC_STATUS_APX 0x02, 0x70, 4 |
| Sub-registers of Register RG_RX_STATUS. More... | |
| #define | SR_TRX_CMD 0x02, 0x1F, 0 |
| Sub-registers of Register RG_TRX_STATE. More... | |
| #define | SR_TRX_OFF_AVDD_EN 0x0C, 0x40, 6 |
| Access parameters for sub-register TRX_OFF_AVDD_EN in register RG_TRX_CTRL_2. More... | |
| #define | SR_TRX_STATUS 0x01, 0x1F, 0 |
| Sub-registers of Register RG_TRX_STATUS. More... | |
| #define | SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 |
| Access parameters for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1. More... | |
| #define | SR_TX_PWR 0x05, 0x1F, 0 |
| Sub-registers of Register RG_PHY_TX_PWR. More... | |
| #define | SR_VERSION_NUM 0x1D, 0xFF, 0 |
| Sub-registers of Register RG_VERSION_NUM. More... | |
| #define | SR_XTAL_MODE 0x12, 0xF0, 4 |
| Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL. More... | |
| #define | SR_XTAL_TRIM 0x12, 0x0F, 0 |
| Sub-registers of Register RG_XOSC_CTRL. More... | |
| #define | TRANSCEIVER_NAME "AT86RF212B" |
| #define | TRX_IRQ_DELAY_US (9) |
| #define | TRX_OFF_AVDD_DISABLE (0) |
| Constant TRX_OFF_AVDD_DISABLE for sub-register SR_TRX_OFF_AVDD_EN in register TRX_CTRL_2. More... | |
| #define | TRX_OFF_AVDD_ENABLE (1) |
| Constant TRX_OFF_AVDD_ENABLE for sub-register SR_TRX_OFF_AVDD_EN in register TRX_CTRL_2. More... | |
| #define | TRX_OFF_TO_PLL_ON_TIME_US (170) |
| #define | TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES (35) |
| #define | TRX_SUPPORTED_CHANNELS (0x000007FF) |
| Parameter definitions. More... | |
| #define | TRX_SUPPORTED_CHANNELS_CHINA (0x0000000F) |
| #define | TX_AUTO_CRC_DISABLE (0) |
| Constant TX_AUTO_CRC_DISABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1. More... | |
| #define | TX_AUTO_CRC_ENABLE (1) |
| Constant TX_AUTO_CRC_ENABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1. More... | |
| #define | TX_PWR_TOLERANCE (0x80) |
| #define | UPLD_RES_FT_DISABLE (0) |
| Constant UPLD_RES_FT_DISABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1. More... | |
| #define | UPLD_RES_FT_ENABLE (1) |
| Constant UPLD_RES_FT_ENABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1. More... | |
| #define | VERSION_NUM_AT86RF12B_C (0x03) |
| Constant VERSION_NUM_AT86RF12B_C for sub-register SR_VERSION_NUM in register VERSION_NUM. More... | |
Typedefs | |
| typedef enum tal_trx_status_tag | tal_trx_status_t |
| sub-register TRX_STATUS in register TRX_STATUS More... | |
| typedef enum trx_cmd_tag | trx_cmd_t |
| Enumerations. More... | |
| typedef enum trx_irq_reason_tag | trx_irq_reason_t |
| sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS More... | |
| typedef enum trx_trac_status_tag | trx_trac_status_t |
| sub-register TRAC_STATUS in register TRX_STATE More... | |
Enumerations | |
| enum | tal_trx_status_tag { P_ON = (0x00), BUSY_RX = (0x01), BUSY_TX = (0x02), RX_ON = (0x06), TRX_OFF = (0x08), PLL_ON = (0x09), TRX_SLEEP = (0x0F), BUSY_RX_AACK = (0x11), BUSY_TX_ARET = (0x12), RX_AACK_ON = (0x16), TX_ARET_ON = (0x19), RX_ON_NOCLK = (0x1C), RX_AACK_ON_NOCLK = (0x1D), BUSY_RX_AACK_NOCLK = (0x1E), STATE_TRANSITION_IN_PROGRESS = (0x1F) } |
| sub-register TRX_STATUS in register TRX_STATUS More... | |
| enum | trx_cmd_tag { CMD_NOP = (0x00), CMD_TX_START = (0x02), CMD_FORCE_TRX_OFF = (0x03), CMD_FORCE_PLL_ON = (0x04), CMD_RX_ON = (0x06), CMD_TRX_OFF = (0x08), CMD_PLL_ON = (0x09), CMD_RX_AACK_ON = (0x16), CMD_TX_ARET_ON = (0x19), CMD_SLEEP = (0x0F) } |
| Enumerations. More... | |
| enum | trx_irq_reason_tag { TRX_IRQ_7_BAT_LOW = (0x80), TRX_IRQ_6_TRX_UR = (0x40), TRX_IRQ_5_AMI = (0x20), TRX_IRQ_4_CCA_ED_DONE = (0x10), TRX_IRQ_3_TRX_END = (0x08), TRX_IRQ_2_RX_START = (0x04), TRX_IRQ_1_PLL_UNLOCK = (0x02), TRX_IRQ_0_PLL_LOCK = (0x01), TRX_NO_IRQ = (0x00) } |
| sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS More... | |
| enum | trx_trac_status_tag { TRAC_SUCCESS = (0x00), TRAC_SUCCESS_DATA_PENDING = (0x01), TRAC_SUCCESS_WAIT_FOR_ACK = (0x02), TRAC_CHANNEL_ACCESS_FAILURE = (0x03), TRAC_NO_ACK = (0x05), TRAC_INVALID = (0x07) } |
| sub-register TRAC_STATUS in register TRX_STATE More... | |
| #define ACK_DISABLE (1) |
Constant ACK_DISABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1.
| #define ACK_ENABLE (0) |
Constant ACK_ENABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1.
| #define ACK_TIME_12_SYMBOLS (0) |
Constant ACK_TIME_12_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1.
Referenced by apply_channel_page_configuration().
| #define ACK_TIME_2_SYMBOLS (1) |
Constant ACK_TIME_2_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1.
Referenced by apply_channel_page_configuration().
| #define AES_BASE_ADDR (0x80) |
Register addresses.
Base address for Transceiver AES address space
Referenced by sal_aes_read(), sal_aes_restart(), sal_aes_setup(), and sal_aes_wrrd().
| #define AES_DIR_DECRYPT (1) |
Constant AES_DIR_DECRYPT for sub-register SR_AES_DIR in register AES_CTRL.
Referenced by sal_aes_setup().
| #define AES_DIR_ENCRYPT (0) |
Constant AES_DIR_ENCRYPT for sub-register SR_AES_DIR in register AES_CTRL.
Referenced by compute_mic(), encrypt_pldmic(), sal_aes_restart(), sal_aes_setup(), and stb_ccm_secure().
| #define AES_DONE (1) |
Constant AES_DONE for sub-register SR_AES_DONE in register AES_STATUS.
| #define AES_ERROR (1) |
Constant AES_ERROR for sub-register SR_AES_ER in register AES_STATUS.
| #define AES_MODE_CBC (2) |
Constant AES_MODE_CBC for sub-register SR_AES_MODE in register AES_CTRL.
Referenced by compute_mic(), and sal_aes_setup().
| #define AES_MODE_ECB (0) |
Constant AES_MODE_ECB for sub-register SR_AES_MODE in register AES_CTRL.
Referenced by compute_mic(), encrypt_pldmic(), sal_aes_setup(), and stb_ccm_secure().
| #define AES_MODE_KEY (1) |
Constant AES_MODE_KEY for sub-register SR_AES_MODE in register AES_CTRL.
Referenced by sal_aes_restart(), and sal_aes_setup().
| #define AES_NO_ERROR (0) |
Constant AES_NO_ERROR for sub-register SR_AES_ER in register AES_STATUS.
| #define AES_NOT_DONE (0) |
Constant AES_NOT_DONE for sub-register SR_AES_DONE in register AES_STATUS.
| #define AES_REQUEST (1) |
Constant AES_REQUEST for sub-register SR_AES_REQUEST in register AES_CTRL.
Referenced by sal_aes_setup().
| #define ALT_SPECTRUM_DISABLE (0) |
Constant ALT_SPECTRUM_DISABLE for sub-register SR_ALT_SPECTRUM in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define ALT_SPECTRUM_ENABLE (1) |
Constant ALT_SPECTRUM_ENABLE for sub-register SR_ALT_SPECTRUM in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define ALTRATE_100_KBPS_OR_250_KBPS (0) |
Constant ALTRATE_100_KBPS_OR_250_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define ALTRATE_200_KBPS_OR_500_KBPS (1) |
Constant ALTRATE_200_KBPS_OR_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define ALTRATE_400_KBPS_OR_1_MBPS (2) |
Constant ALTRATE_400_KBPS_OR_1_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define ANT_CTRL_1 (1) |
Constant ANT_CTRL_1 for sub-register SR_ANT_CTRL in register ANT_DIV.
Referenced by tal_ant_div_config().
| #define ANT_CTRL_2 (2) |
Constant ANT_CTRL_2 for sub-register SR_ANT_CTRL in register ANT_DIV.
Referenced by tal_ant_div_config().
| #define ANT_DIV_DISABLE (0) |
Constant ANT_DIV_DISABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV.
Referenced by tal_ant_div_config().
| #define ANT_DIV_ENABLE (1) |
Constant ANT_DIV_ENABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV.
Referenced by tal_ant_div_config().
| #define ANT_EXT_SW_DISABLE (0) |
Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV.
Referenced by set_trx_state(), and tal_ant_div_config().
| #define ANT_EXT_SW_ENABLE (1) |
Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV.
Referenced by set_trx_state(), tal_ant_div_config(), and trx_config().
| #define ANT_SEL_ANTENNA_0 (0) |
Constant ANT_SEL_ANTENNA_0 for sub-register SR_ANT_SEL in register ANT_DIV.
| #define ANT_SEL_ANTENNA_1 (1) |
Constant ANT_SEL_ANTENNA_1 for sub-register SR_ANT_SEL in register ANT_DIV.
| #define BATMON_HR_HIGH (1) |
Constant BATMON_HR_HIGH for sub-register SR_BATMON_HR in register BATMON.
| #define BATMON_HR_LOW (0) |
Constant BATMON_HR_LOW for sub-register SR_BATMON_HR in register BATMON.
| #define BATMON_NOT_VALID (0) |
Constant BATMON_NOT_VALID for sub-register SR_BATMON_OK in register BATMON.
| #define BATMON_VALID (1) |
Constant BATMON_VALID for sub-register SR_BATMON_OK in register BATMON.
| #define BPSK_MODE (0) |
Constant BPSK_MODE for sub-register SR_BPSK_OQPSK in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define BPSK_TX_OFFSET (3) |
Referenced by apply_channel_page_configuration().
| #define CCA_CH_BUSY (0) |
Constant CCA_CH_BUSY for sub-register SR_CCA_STATUS in register TRX_STATUS.
| #define CCA_CH_IDLE (1) |
Constant CCA_CH_IDLE for sub-register SR_CCA_STATUS in register TRX_STATUS.
Referenced by perform_cca_twice().
| #define CCA_COMPLETED (1) |
Constant CCA_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS.
Referenced by perform_cca_twice().
| #define CCA_CS_THRES_15 (0xF) |
Constant CCA_CS_THRES_15 for sub-register SR_CCA_CS_THRES in register CCA_THRES.
| #define CCA_CS_THRES_7 (0x7) |
Constant CCA_CS_THRES_7 for sub-register SR_CCA_CS_THRES in register CCA_THRES.
| #define CCA_DETECTION_TIME_SYMBOL (8) |
| #define CCA_DURATION_SYM |
Referenced by perform_cca_twice().
| #define CCA_MODE_0 (0) |
Constant CCA_MODE_0 for sub-register SR_CCA_MODE in register PHY_CC_CCA.
| #define CCA_MODE_1 (1) |
Constant CCA_MODE_1 for sub-register SR_CCA_MODE in register PHY_CC_CCA.
| #define CCA_MODE_2 (2) |
Constant CCA_MODE_2 for sub-register SR_CCA_MODE in register PHY_CC_CCA.
| #define CCA_MODE_3 (3) |
Constant CCA_MODE_3 for sub-register SR_CCA_MODE in register PHY_CC_CCA.
| #define CCA_NO_START (0) |
Constant CCA_NO_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA.
| #define CCA_ONGOING (0) |
Constant CCA_ONGOING for sub-register SR_CCA_DONE in register TRX_STATUS.
| #define CCA_PRE_START_DURATION_US (20) |
Referenced by perform_cca_twice().
| #define CCA_PREPARATION_DURATION_US (50) |
Referenced by csma_backoff_calculation(), and perform_cca_twice().
| #define CCA_PROCESS_TIME_SYM (1) |
| #define CCA_PROCESS_TIME_US (12) |
| #define CCA_START (1) |
Constant CCA_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA.
Referenced by perform_cca_twice().
| #define CLEAR_PD (0) |
Constant CLEAR_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1.
| #define CLKM_16MHZ (5) |
Constant CLKM_16MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CLKM_1_4MHZ (6) |
Constant CLKM_1_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CLKM_1MHZ (1) |
Constant CLKM_1MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CLKM_2MHZ (2) |
Constant CLKM_2MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CLKM_4MHZ (3) |
Constant CLKM_4MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CLKM_8MHZ (4) |
Constant CLKM_8MHZ for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CLKM_NO_CLOCK (0) |
Constant CLKM_NO_CLOCK for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CLKM_SHA_DISABLE (0) |
Constant CLKM_SHA_DISABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0.
Referenced by trx_config().
| #define CLKM_SHA_ENABLE (1) |
Constant CLKM_SHA_ENABLE for sub-register SR_CLKM_SHA_SEL in register TRX_CTRL_0.
| #define CLKM_SYMBOL_RATE (7) |
Constant CLKM_SYMBOL_RATE for sub-register SR_CLKM_CTRL in register TRX_CTRL_0.
| #define CRC16_NOT_VALID (0) |
Constant CRC16_NOT_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI.
Referenced by handle_received_frame_irq().
| #define CRC16_VALID (1) |
Constant CRC16_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI.
| #define CSMA_MODE_ENABLE (0) |
Constant CSMA_MODE_ENABLE for sub-register SR_CSMA_LBT_MODE in register XAH_CTRL_1.
| #define EXT_FRONTEND_DISABLE (0) |
Constant EXT_FRONTEND_DISABLE for sub-register SR_PA_EXT_EN in register TRX_CTRL_1.
| #define EXT_FRONTEND_ENABLE (1) |
Constant EXT_FRONTEND_ENABLE for sub-register SR_PA_EXT_EN in register TRX_CTRL_1.
| #define FLTR_RES_FT_DISABLE (0) |
Constant FLTR_RES_FT_DISABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1.
| #define FLTR_RES_FT_ENABLE (1) |
Constant FLTR_RES_FT_ENABLE for sub-register SR_AACK_FLTR_RES_FT in register XAH_CTRL_1.
| #define FRAME_VERSION_00 (0) |
Constant FRAME_VERSION_00 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.
| #define FRAME_VERSION_01 (1) |
Constant FRAME_VERSION_01 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.
| #define FRAME_VERSION_012 (2) |
Constant FRAME_VERSION_012 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.
| #define FRAME_VERSION_IGNORED (3) |
Constant FRAME_VERSION_IGNORED for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.
| #define HIGH_DATA_RATE (1) |
Constant HIGH_DATA_RATE for sub-register SR_SUB_MODE in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define I_AM_COORD_DISABLE (0) |
Constant I_AM_COORD_DISABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1.
| #define I_AM_COORD_ENABLE (1) |
Constant I_AM_COORD_ENABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1.
| #define IEEE_CHANNEL_0 (0x00) |
Constant IEEE_CHANNEL_0 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_1 (0x01) |
Constant IEEE_CHANNEL_1 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_10 (0x0A) |
Constant IEEE_CHANNEL_10 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_2 (0x02) |
Constant IEEE_CHANNEL_2 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_3 (0x03) |
Constant IEEE_CHANNEL_3 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_4 (0x04) |
Constant IEEE_CHANNEL_4 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_5 (0x05) |
Constant IEEE_CHANNEL_5 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_6 (0x06) |
Constant IEEE_CHANNEL_6 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_7 (0x07) |
Constant IEEE_CHANNEL_7 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_8 (0x08) |
Constant IEEE_CHANNEL_8 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IEEE_CHANNEL_9 (0x09) |
Constant IEEE_CHANNEL_9 for sub-register SR_CHANNEL in register PHY_CC_CCA.
| #define IF_SHIFT_MODE_AUTO (1) |
Constant IF_SHIFT_MODE_AUTO for sub-register SR_IF_SHIFT_MODE in register RF_CTRL_0.
| #define IF_SHIFT_MODE_OFF (0) |
Constant IF_SHIFT_MODE_OFF for sub-register SR_IF_SHIFT_MODE in register RF_CTRL_0.
| #define IRQ_HIGH_ACTIVE (0) |
Constant IRQ_HIGH_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1.
| #define IRQ_LOW_ACTIVE (1) |
Constant IRQ_LOW_ACTIVE for sub-register SR_IRQ_POLARITY in register TRX_CTRL_1.
| #define IRQ_MASK_MODE_OFF (0) |
Constant IRQ_MASK_MODE_OFF for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1.
| #define IRQ_MASK_MODE_ON (1) |
Constant IRQ_MASK_MODE_ON for sub-register SR_IRQ_MASK_MODE in register TRX_CTRL_1.
Referenced by trx_config().
| #define JCM_DISABLE (0) |
Constant JCM_DISABLE for sub-register SR_JCM_EN in register RX_CTRL.
| #define JCM_ENABLE (1) |
Constant JCM_ENABLE for sub-register SR_JCM_EN in register RX_CTRL.
| #define LBT_MODE_ENABLE (1) |
Constant LBT_MODE_ENABLE for sub-register SR_CSMA_LBT_MODE in register XAH_CTRL_1.
| #define LOW_DATA_RATE (0) |
Constant LOW_DATA_RATE for sub-register SR_SUB_MODE in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define NEWRATE_500_KBPS (3) |
Constant NEWRATE_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.
| #define OQPSK_MODE (1) |
Constant OQPSK_MODE for sub-register SR_BPSK_OQPSK in register TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define OQPSK_SCRAM_DISABLE (0) |
Constant OQPSK_SCRAM_DISABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2.
| #define OQPSK_SCRAM_ENABLE (1) |
Constant OQPSK_SCRAM_ENABLE for sub-register SR_OQPSK_SCRAM_EN in register TRX_CTRL_2.
| #define OQPSK_TX_OFFSET (2) |
Constant OQPSK_TX_OFFSET for sub-register SR_GC_TX_OFFS in register RF_CTRL_0.
Referenced by apply_channel_page_configuration().
| #define P_ON_TO_CLKM_AVAILABLE_MAX_US (1000) |
| #define P_ON_TO_CLKM_AVAILABLE_TYP_US (420) |
Referenced by trx_init().
| #define PA_BOOST_DISABLE (0) |
Constant PA_BOOST_DISABLE for sub-register SR_PA_BOOST in register PHY_TX_PWR.
| #define PA_BOOST_ENABLE (1) |
Constant PA_BOOST_ENABLE for sub-register SR_PA_BOOST in register PHY_TX_PWR.
| #define PAD_CLKM_2_MA (0) |
Constant PAD_CLKM_2_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0.
Referenced by trx_config().
| #define PAD_CLKM_4_MA (1) |
Constant PAD_CLKM_4_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0.
| #define PAD_CLKM_6_MA (2) |
Constant PAD_CLKM_6_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0.
| #define PAD_CLKM_8_MA (3) |
Constant PAD_CLKM_8_MA for sub-register SR_PAD_IO_CLKM in register TRX_CTRL_0.
| #define PAD_IO_2_MA (0) |
Constant PAD_IO_2_MA for sub-register SR_PAD_IO in register TRX_CTRL_0.
| #define PAD_IO_4_MA (1) |
Constant PAD_IO_4_MA for sub-register SR_PAD_IO in register TRX_CTRL_0.
| #define PAD_IO_6_MA (2) |
Constant PAD_IO_6_MA for sub-register SR_PAD_IO in register TRX_CTRL_0.
| #define PAD_IO_8_MA (3) |
Constant PAD_IO_8_MA for sub-register SR_PAD_IO in register TRX_CTRL_0.
| #define PART_NUM_AT86RF212B (0x07) |
Constant PART_NUM_AT86RF212B for sub-register SR_PART_NUM in register PART_NUM.
Referenced by trx_init().
| #define PRE_TX_DURATION_US (32) |
Referenced by send_frame(), and send_frame_at_next_backoff_boundary().
| #define PROM_MODE_DISABLE (0) |
Constant PROM_MODE_DISABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1.
| #define PROM_MODE_ENABLE (1) |
Constant PROM_MODE_ENABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1.
| #define RG_AES_CTRL (0x03) |
Offset for register AES_CTRL.
Referenced by sal_aes_restart(), sal_aes_setup(), and sal_aes_wrrd().
| #define RG_AES_CTRL_MIRROR (0x14) |
Offset for register AES_CTRL_MIRROR.
| #define RG_AES_STATE_KEY_0 (0x04) |
Offset for register AES_STATE_KEY_0.
Referenced by sal_aes_read(), sal_aes_setup(), and sal_aes_wrrd().
| #define RG_AES_STATUS (0x02) |
Offset for register AES_STATUS.
| #define RG_ANT_DIV (0x0D) |
Offset for register ANT_DIV.
| #define RG_BATMON (0x11) |
Offset for register BATMON.
| #define RG_CC_CTRL_0 (0x13) |
Offset for register CC_CTRL_0.
Referenced by tal_get_curr_trx_config(), tal_set_frequency(), and tal_set_frequency_regs().
| #define RG_CC_CTRL_1 (0x14) |
Offset for register CC_CTRL_1.
| #define RG_CCA_THRES (0x09) |
Offset for register CCA_THRES.
| #define RG_CSMA_BE (0x2F) |
Offset for register CSMA_BE.
| #define RG_CSMA_SEED_0 (0x2D) |
Offset for register CSMA_SEED_0.
Referenced by set_trx_state(), and trx_config().
| #define RG_CSMA_SEED_1 (0x2E) |
Offset for register CSMA_SEED_1.
| #define RG_ED (0x01) |
Offset for register ED.
| #define RG_FTN_CTRL (0x18) |
Offset for register FTN_CTRL.
| #define RG_IEEE_ADDR_0 (0x24) |
Offset for register IEEE_ADDR_0.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define RG_IEEE_ADDR_1 (0x25) |
Offset for register IEEE_ADDR_1.
| #define RG_IEEE_ADDR_2 (0x26) |
Offset for register IEEE_ADDR_2.
| #define RG_IEEE_ADDR_3 (0x27) |
Offset for register IEEE_ADDR_3.
| #define RG_IEEE_ADDR_4 (0x28) |
Offset for register IEEE_ADDR_4.
| #define RG_IEEE_ADDR_5 (0x29) |
Offset for register IEEE_ADDR_5.
| #define RG_IEEE_ADDR_6 (0x2A) |
Offset for register IEEE_ADDR_6.
| #define RG_IEEE_ADDR_7 (0x2B) |
Offset for register IEEE_ADDR_7.
| #define RG_IRQ_MASK (0x0E) |
Offset for register IRQ_MASK.
Referenced by ed_scan_done(), set_trx_state(), tal_ed_start(), trx_config(), and trx_init().
| #define RG_IRQ_STATUS (0x0F) |
Offset for register IRQ_STATUS.
Referenced by perform_cca_twice(), set_trx_state(), switch_pll_on(), tal_ed_start(), tal_generate_rand_seed(), trx_ed_irq_handler_cb(), trx_irq_awake_handler_cb(), and trx_irq_handler_cb().
| #define RG_LQI (0x00) |
Offset for register LQI.
| #define RG_MAN_ID_0 (0x1E) |
Offset for register MAN_ID_0.
| #define RG_MAN_ID_1 (0x1F) |
Offset for register MAN_ID_1.
| #define RG_PAN_ID_0 (0x22) |
Offset for register PAN_ID_0.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define RG_PAN_ID_1 (0x23) |
Offset for register PAN_ID_1.
| #define RG_PART_NUM (0x1C) |
Offset for register PART_NUM.
Referenced by trx_init().
| #define RG_PHY_CC_CCA (0x08) |
Offset for register PHY_CC_CCA.
| #define RG_PHY_ED_LEVEL (0x07) |
Offset for register PHY_ED_LEVEL.
Referenced by handle_received_frame_irq(), tal_ed_start(), and trx_ed_irq_handler_cb().
| #define RG_PHY_RSSI (0x06) |
Offset for register PHY_RSSI.
| #define RG_PHY_TX_PWR (0x05) |
Offset for register PHY_TX_PWR.
Referenced by set_default_tx_pwr(), tal_pib_set(), and write_all_tal_pib_to_trx().
| #define RG_PLL_CF (0x1A) |
Offset for register PLL_CF.
| #define RG_PLL_DCU (0x1B) |
Offset for register PLL_DCU.
| #define RG_RF_CTRL_0 (0x16) |
Offset for register RF_CTRL_0.
| #define RG_RX_CTRL (0x0A) |
Offset for register RX_CTRL.
| #define RG_RX_STATUS (0x02) |
Offset for register RX_STATUS.
| #define RG_RX_SYN (0x15) |
Offset for register RX_SYN.
| #define RG_SFD_VALUE (0x0B) |
Offset for register SFD_VALUE.
| #define RG_SHORT_ADDR_0 (0x20) |
Offset for register SHORT_ADDR_0.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define RG_SHORT_ADDR_1 (0x21) |
Offset for register SHORT_ADDR_1.
| #define RG_TRX_CTRL_0 (0x03) |
Offset for register TRX_CTRL_0.
| #define RG_TRX_CTRL_1 (0x04) |
Offset for register TRX_CTRL_1.
| #define RG_TRX_CTRL_2 (0x0C) |
Offset for register TRX_CTRL_2.
| #define RG_TRX_STATE (0x02) |
Offset for register TRX_STATE.
Referenced by set_trx_state(), switch_pll_on(), and trx_init().
| #define RG_TRX_STATUS (0x01) |
Offset for register TRX_STATUS.
| #define RG_VERSION_NUM (0x1D) |
Offset for register VERSION_NUM.
| #define RG_VREG_CTRL (0x10) |
Offset for register VREG_CTRL.
| #define RG_XAH_CTRL_0 (0x2C) |
Offset for register XAH_CTRL_0.
| #define RG_XAH_CTRL_1 (0x17) |
Offset for register XAH_CTRL_1.
| #define RG_XOSC_CTRL (0x12) |
Offset for register XOSC_CTRL.
| #define RSSI_BASE_VAL_BPSK_300_DBM (-100) |
Referenced by tal_get_rssi_base_val().
| #define RSSI_BASE_VAL_BPSK_600_DBM (-99) |
| #define RSSI_BASE_VAL_OQPSK_1000_RC_DBM (-98) |
| #define RSSI_BASE_VAL_OQPSK_1000_SIN_DBM (-99) |
| #define RSSI_BASE_VAL_OQPSK_400_RC_DBM (-98) |
Referenced by tal_get_rssi_base_val().
| #define RSSI_BASE_VAL_OQPSK_400_SIN_RC_DBM (-98) |
Referenced by tal_get_rssi_base_val().
| #define RST_PULSE_WIDTH_NS (625) |
Typical timing values.
| #define RST_PULSE_WIDTH_US |
Referenced by trx_init(), and trx_reset().
| #define RX_BL_CTRL_DISABLE (0) |
Constant RX_BL_CTRL_DISABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1.
| #define RX_BL_CTRL_ENABLE (1) |
Constant RX_BL_CTRL_ENABLE for sub-register SR_RX_BL_CTRL in register TRX_CTRL_1.
| #define RX_DISABLE (1) |
Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.
Referenced by perform_cca_twice(), and tal_ed_start().
| #define RX_ENABLE (0) |
Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.
Referenced by ed_scan_done(), perform_cca_twice(), tal_ed_start(), and tal_generate_rand_seed().
| #define RX_SAFE_MODE_DISABLE (0) |
Constant RX_SAFE_MODE_DISABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2.
| #define RX_SAFE_MODE_ENABLE (1) |
Constant RX_SAFE_MODE_ENABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2.
Referenced by trx_config().
| #define RX_TIMESTAMPING_DISABLE (0) |
Constant RX_TIMESTAMPING_DISABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1.
| #define RX_TIMESTAMPING_ENABLE (1) |
Constant RX_TIMESTAMPING_ENABLE for sub-register SR_IRQ_2_EXT_EN in register TRX_CTRL_1.
Referenced by trx_config().
| #define RXAPPENDIX_BASE_ADDR (0x00) |
Base address and size for RX frame appendix.
| #define RXAPPENDIX_SIZE (3) |
| #define RXO_DISABLE (0) |
Constant RXO_DISABLE for sub-register SR_RX_OVERRIDE in register RX_SYN.
| #define RXO_ENABLE (6) |
Constant RXO_ENABLE for sub-register SR_RX_OVERRIDE in register RX_SYN.
Referenced by trx_config().
| #define SET_PD (1) |
Constant SET_PD for sub-register SR_AACK_SET_PD in register CSMA_SEED_1.
Referenced by trx_config().
| #define SLEEP_TO_TRX_OFF_MAX_US (1000) |
| #define SLEEP_TO_TRX_OFF_TYP_US (420) |
Referenced by csma_backoff_calculation(), perform_cca_twice(), and trx_reset().
| #define SPI_CMD_MODE_DEFAULT (0) |
Constant SPI_CMD_MODE_DEFAULT for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.
| #define SPI_CMD_MODE_IRQ_STATUS (3) |
Constant SPI_CMD_MODE_IRQ_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.
| #define SPI_CMD_MODE_PHY_RSSI (2) |
Constant SPI_CMD_MODE_PHY_RSSI for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.
| #define SPI_CMD_MODE_TRX_STATUS (1) |
Constant SPI_CMD_MODE_TRX_STATUS for sub-register SR_SPI_CMD_MODE in register TRX_CTRL_1.
| #define SR_AACK_ACK_TIME 0x17, 0x04, 2 |
Access parameters for sub-register AACK_ACK_TIME in register RG_XAH_CTRL_1.
Referenced by apply_channel_page_configuration().
| #define SR_AACK_DIS_ACK 0x2E, 0x10, 4 |
Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1.
| #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 |
Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1.
| #define SR_AACK_FVN_MODE 0x2E, 0xC0, 6 |
Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.
| #define SR_AACK_I_AM_COORD 0x2E, 0x08, 3 |
Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_AACK_PROM_MODE 0x17, 0x02, 1 |
Sub-registers of Register RG_XAH_CTRL_1.
Access parameters for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1
Referenced by tal_get_curr_trx_config(), and tal_rxaack_prom_mode_ctrl().
| #define SR_AACK_SET_PD 0x2E, 0x20, 5 |
Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.
Referenced by trx_config().
| #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 |
Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1.
| #define SR_AES_DIR 0x03, 0x08, 3 |
Sub-registers of Register RG_AES_CTRL.
Access parameters for sub-register AES_DIR in register RG_AES_CTRL
Referenced by sal_aes_setup().
| #define SR_AES_DONE 0x02, 0x01, 0 |
Sub-registers of Register RG_AES_STATUS.
Access parameters for sub-register AES_DONE in register RG_AES_STATUS
| #define SR_AES_ER 0x02, 0x80, 7 |
Access parameters for sub-register AES_ER in register RG_AES_STATUS.
| #define SR_AES_MODE 0x03, 0x70, 4 |
Access parameters for sub-register AES_MODE in register RG_AES_CTRL.
Referenced by sal_aes_restart(), and sal_aes_setup().
| #define SR_AES_REQUEST 0x03, 0x80, 7 |
Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL.
Referenced by sal_aes_setup().
| #define SR_ALT_SPECTRUM 0x0C, 0x10, 4 |
Access parameters for sub-register ALT_SPECTRUM in register RG_TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define SR_ANT_CTRL 0x0D, 0x03, 0 |
Sub-registers of Register RG_ANT_DIV.
Access parameters for sub-register ANT_CTRL in register RG_ANT_DIV
Referenced by tal_ant_div_config(), tal_get_curr_trx_config(), and trx_config().
| #define SR_ANT_DIV_EN 0x0D, 0x08, 3 |
Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV.
Referenced by tal_ant_div_config(), and tal_get_curr_trx_config().
| #define SR_ANT_EXT_SW_EN 0x0D, 0x04, 2 |
Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV.
Referenced by set_trx_state(), tal_ant_div_config(), and trx_config().
| #define SR_ANT_SEL 0x0D, 0x80, 7 |
Access parameters for sub-register ANT_SEL in register RG_ANT_DIV.
Referenced by tal_get_curr_trx_config().
| #define SR_AVDD_OK 0x10, 0x40, 6 |
Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL.
| #define SR_AVREG_EXT 0x10, 0x80, 7 |
Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL.
| #define SR_BATMON_HR 0x11, 0x10, 4 |
Access parameters for sub-register BATMON_HR in register RG_BATMON.
| #define SR_BATMON_OK 0x11, 0x20, 5 |
Access parameters for sub-register BATMON_OK in register RG_BATMON.
| #define SR_BATMON_VTH 0x11, 0x0F, 0 |
| #define SR_BPSK_OQPSK 0x0C, 0x08, 3 |
Access parameters for sub-register BPSK_OQPSK in register RG_TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define SR_CC_BAND 0x14, 0x07, 0 |
Sub-registers of Register RG_CC_CTRL_1.
Access parameters for sub-register CC_BAND in register RG_CC_CTRL_1
Referenced by apply_channel_page_configuration(), tal_get_curr_trx_config(), tal_set_frequency(), and tal_set_frequency_regs().
| #define SR_CC_NUMBER 0x13, 0xFF, 0 |
Sub-registers of Register RG_CC_CTRL_0.
Access parameters for sub-register CC_NUMBER in register RG_CC_CTRL_0
Referenced by apply_channel_page_configuration(), and tal_pib_set().
| #define SR_CCA_CS_THRES 0x09, 0xF0, 4 |
Access parameters for sub-register CCA_CS_THRES in register RG_CCA_THRES.
| #define SR_CCA_DONE 0x01, 0x80, 7 |
Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS.
Referenced by perform_cca_twice().
| #define SR_CCA_ED_THRES 0x09, 0x0F, 0 |
Sub-registers of Register RG_CCA_THRES.
Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES
Referenced by trx_config().
| #define SR_CCA_MODE 0x08, 0x60, 5 |
Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_CCA_REQUEST 0x08, 0x80, 7 |
Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA.
Referenced by perform_cca_twice().
| #define SR_CCA_STATUS 0x01, 0x40, 6 |
Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS.
Referenced by perform_cca_twice().
| #define SR_CHANNEL 0x08, 0x1F, 0 |
Sub-registers of Register RG_PHY_CC_CCA.
Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA
Referenced by apply_channel_page_configuration(), and tal_pib_set().
| #define SR_CLKM_CTRL 0x03, 0x07, 0 |
Sub-registers of Register RG_TRX_CTRL_0.
Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0
| #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 |
Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0.
Referenced by trx_config().
| #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 |
Access parameters for sub-register CSMA_LBT_MODE in register RG_XAH_CTRL_1.
| #define SR_CSMA_SEED_0 0x2D, 0xFF, 0 |
Sub-registers of Register RG_CSMA_SEED_0.
Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0
| #define SR_CSMA_SEED_1 0x2E, 0x07, 0 |
Sub-registers of Register RG_CSMA_SEED_1.
Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1
Referenced by set_trx_state(), and trx_config().
| #define SR_DVDD_OK 0x10, 0x04, 2 |
Sub-registers of Register RG_VREG_CTRL.
Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL
| #define SR_DVREG_EXT 0x10, 0x08, 3 |
Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL.
| #define SR_ED_APX 0x01, 0xFF, 0 |
| #define SR_ED_LEVEL 0x07, 0xFF, 0 |
Sub-registers of Register RG_PHY_ED_LEVEL.
Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL
| #define SR_FTN_START 0x18, 0x80, 7 |
Sub-registers of Register RG_FTN_CTRL.
Access parameters for sub-register FTN_START in register RG_FTN_CTRL
| #define SR_GC_PA 0x05, 0x60, 5 |
Access parameters for sub-register GC_PA in register RG_PHY_TX_PWR.
| #define SR_GC_TX_OFFS 0x16, 0x03, 0 |
Sub-registers of Register RG_RF_CTRL_0.
Access parameters for sub-register GC_TX_OFFS in register RG_RF_CTRL_0
Referenced by apply_channel_page_configuration().
| #define SR_IEEE_ADDR_0 0x24, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_0.
Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0
| #define SR_IEEE_ADDR_1 0x25, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_1.
Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1
| #define SR_IEEE_ADDR_2 0x26, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_2.
Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2
| #define SR_IEEE_ADDR_3 0x27, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_3.
Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3
| #define SR_IEEE_ADDR_4 0x28, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_4.
Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4
| #define SR_IEEE_ADDR_5 0x29, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_5.
Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5
| #define SR_IEEE_ADDR_6 0x2A, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_6.
Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6
| #define SR_IEEE_ADDR_7 0x2B, 0xFF, 0 |
Sub-registers of Register RG_IEEE_ADDR_7.
Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7
| #define SR_IF_SHIFT_MODE 0x16, 0x0C, 2 |
Access parameters for sub-register IF_SHIFT_MODE in register RG_RF_CTRL_0.
| #define SR_IRQ_0_PLL_LOCK 0x0F, 0x01, 0 |
Sub-registers of Register RG_IRQ_STATUS.
Access parameters for sub-register IRQ_0_PLL_LOCK in register RG_IRQ_STATUS
| #define SR_IRQ_1_PLL_UNLOCK 0x0F, 0x02, 1 |
Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS.
| #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 |
Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1.
Referenced by trx_config().
| #define SR_IRQ_2_RX_START 0x0F, 0x04, 2 |
Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS.
| #define SR_IRQ_3_TRX_END 0x0F, 0x08, 3 |
Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS.
| #define SR_IRQ_4_CCA_ED_DONE 0x0F, 0x10, 4 |
Access parameters for sub-register IRQ_4_CCA_ED_DONE in register RG_IRQ_STATUS.
| #define SR_IRQ_5_AMI 0x0F, 0x20, 5 |
Access parameters for sub-register IRQ_5_AMI in register RG_IRQ_STATUS.
| #define SR_IRQ_6_TRX_UR 0x0F, 0x40, 6 |
Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS.
| #define SR_IRQ_7_BAT_LOW 0x0F, 0x80, 7 |
Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS.
| #define SR_IRQ_MASK 0x0E, 0xFF, 0 |
Sub-registers of Register RG_IRQ_MASK.
Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK
Referenced by set_trx_state(), and tal_ed_start().
| #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 |
Access parameters for sub-register IRQ_MASK_MODE in register RG_TRX_CTRL_1.
Referenced by trx_config().
| #define SR_IRQ_POLARITY 0x04, 0x01, 0 |
Sub-registers of Register RG_TRX_CTRL_1.
Access parameters for sub-register IRQ_POLARITY in register RG_TRX_CTRL_1
| #define SR_JCM_EN 0x0A, 0x20, 5 |
Sub-registers of Register RG_RX_CTRL.
Access parameters for sub-register JCM_EN in register RG_RX_CTRL
| #define SR_LQI_APX 0x00, 0xFF, 0 |
| #define SR_MAN_ID_0 0x1E, 0xFF, 0 |
Sub-registers of Register RG_MAN_ID_0.
Access parameters for sub-register MAN_ID_0 in register RG_MAN_ID_0
| #define SR_MAN_ID_1 0x1F, 0xFF, 0 |
Sub-registers of Register RG_MAN_ID_1.
Access parameters for sub-register MAN_ID_1 in register RG_MAN_ID_1
| #define SR_MAX_BE 0x2F, 0xF0, 4 |
Access parameters for sub-register MAX_BE in register RG_CSMA_BE.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_MAX_CSMA_RETRIES 0x2C, 0x0E, 1 |
Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0.
Referenced by send_frame(), and write_all_tal_pib_to_trx().
| #define SR_MAX_FRAME_RETRIES 0x2C, 0xF0, 4 |
Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0.
Referenced by send_frame(), and write_all_tal_pib_to_trx().
| #define SR_MIN_BE 0x2F, 0x0F, 0 |
Sub-registers of Register RG_CSMA_BE.
Access parameters for sub-register MIN_BE in register RG_CSMA_BE
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_OQPSK_DATA_RATE 0x0C, 0x03, 0 |
Sub-registers of Register RG_TRX_CTRL_2.
Access parameters for sub-register OQPSK_DATA_RATE in register RG_TRX_CTRL_2
Referenced by apply_channel_page_configuration().
| #define SR_OQPSK_SCRAM_EN 0x0C, 0x20, 5 |
Access parameters for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2.
| #define SR_PA_BOOST 0x05, 0x80, 7 |
Access parameters for sub-register PA_BOOST in register RG_PHY_TX_PWR.
| #define SR_PA_EXT_EN 0x04, 0x80, 7 |
Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1.
Referenced by tal_ext_pa_ctrl().
| #define SR_PA_LT 0x16, 0xC0, 6 |
Access parameters for sub-register PA_LT in register RG_RF_CTRL_0.
| #define SR_PAD_IO 0x03, 0xC0, 6 |
Access parameters for sub-register PAD_IO in register RG_TRX_CTRL_0.
| #define SR_PAD_IO_CLKM 0x03, 0x30, 4 |
Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0.
Referenced by trx_config().
| #define SR_PAN_ID_0 0x22, 0xFF, 0 |
Sub-registers of Register RG_PAN_ID_0.
Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0
| #define SR_PAN_ID_1 0x23, 0xFF, 0 |
Sub-registers of Register RG_PAN_ID_1.
Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1
| #define SR_PART_NUM 0x1C, 0xFF, 0 |
Sub-registers of Register RG_PART_NUM.
Access parameters for sub-register PART_NUM in register RG_PART_NUM
| #define SR_PLL_CF_START 0x1A, 0x80, 7 |
| #define SR_PLL_DCU_START 0x1B, 0x80, 7 |
Sub-registers of Register RG_PLL_DCU.
Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU
| #define SR_PLL_LOCK_CP 0x11, 0x80, 7 |
Access parameters for sub-register PLL_LOCK_CP in register RG_BATMON.
| #define SR_RND_VALUE 0x06, 0x60, 5 |
Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI.
Referenced by tal_generate_rand_seed().
| #define SR_RSSI 0x06, 0x1F, 0 |
Sub-registers of Register RG_PHY_RSSI.
Access parameters for sub-register RSSI in register RG_PHY_RSSI
| #define SR_RX_BL_CTRL 0x04, 0x10, 4 |
Access parameters for sub-register RX_BL_CTRL in register RG_TRX_CTRL_1.
| #define SR_RX_CRC_VALID 0x06, 0x80, 7 |
Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI.
Referenced by handle_received_frame_irq().
| #define SR_RX_CRC_VALID_APX 0x02, 0x80, 7 |
Access parameters for sub-register RX_CRC_VALID_APX in register RG_RX_STATUS.
| #define SR_RX_OVERRIDE 0x15, 0x70, 4 |
Access parameters for sub-register RX_OVERRIDE in register RG_RX_SYN.
Referenced by trx_config().
| #define SR_RX_PDT_DIS 0x15, 0x80, 7 |
Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN.
Referenced by ed_scan_done(), perform_cca_twice(), tal_ed_start(), and tal_generate_rand_seed().
| #define SR_RX_PDT_LEVEL 0x15, 0x0F, 0 |
Sub-registers of Register RG_RX_SYN.
Access parameters for sub-register RX_PDT_LEVEL in register RG_RX_SYN
Referenced by tal_set_rx_sensitivity_level().
| #define SR_RX_SAFE_MODE 0x0C, 0x80, 7 |
Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2.
Referenced by tal_rxsafe_mode_ctrl(), and trx_config().
| #define SR_SFD_VALUE 0x0B, 0xFF, 0 |
Sub-registers of Register RG_SFD_VALUE.
Access parameters for sub-register SFD_VALUE in register RG_SFD_VALUE
| #define SR_SHORT_ADDR_0 0x20, 0xFF, 0 |
Sub-registers of Register RG_SHORT_ADDR_0.
Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0
| #define SR_SHORT_ADDR_1 0x21, 0xFF, 0 |
Sub-registers of Register RG_SHORT_ADDR_1.
Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1
| #define SR_SLOTTED_OPERATION 0x2C, 0x01, 0 |
Sub-registers of Register RG_XAH_CTRL_0.
Access parameters for sub-register SLOTTED_OPERATION in register RG_XAH_CTRL_0
| #define SR_SPI_CMD_MODE 0x04, 0x0C, 2 |
Access parameters for sub-register SPI_CMD_MODE in register RG_TRX_CTRL_1.
| #define SR_SUB_MODE 0x0C, 0x04, 2 |
Access parameters for sub-register SUB_MODE in register RG_TRX_CTRL_2.
Referenced by apply_channel_page_configuration().
| #define SR_TRAC_STATUS 0x02, 0xE0, 5 |
Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE.
Referenced by handle_tx_end_irq().
| #define SR_TRAC_STATUS_APX 0x02, 0x70, 4 |
Sub-registers of Register RG_RX_STATUS.
Access parameters for sub-register TRAC_STATUS_APX in register RG_RX_STATUS
| #define SR_TRX_CMD 0x02, 0x1F, 0 |
Sub-registers of Register RG_TRX_STATE.
Access parameters for sub-register TRX_CMD in register RG_TRX_STATE
| #define SR_TRX_OFF_AVDD_EN 0x0C, 0x40, 6 |
Access parameters for sub-register TRX_OFF_AVDD_EN in register RG_TRX_CTRL_2.
| #define SR_TRX_STATUS 0x01, 0x1F, 0 |
Sub-registers of Register RG_TRX_STATUS.
Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS
Referenced by set_trx_state(), switch_pll_on(), tal_get_trx_status(), trx_init(), and trx_reset().
| #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 |
Access parameters for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1.
| #define SR_TX_PWR 0x05, 0x1F, 0 |
Sub-registers of Register RG_PHY_TX_PWR.
Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR
Referenced by tal_get_curr_trx_config().
| #define SR_VERSION_NUM 0x1D, 0xFF, 0 |
Sub-registers of Register RG_VERSION_NUM.
Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM
| #define SR_XTAL_MODE 0x12, 0xF0, 4 |
Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL.
| #define SR_XTAL_TRIM 0x12, 0x0F, 0 |
Sub-registers of Register RG_XOSC_CTRL.
Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL
| #define TRANSCEIVER_NAME "AT86RF212B" |
| #define TRX_IRQ_DELAY_US (9) |
Referenced by send_frame(), and tx_done_handling().
| #define TRX_OFF_AVDD_DISABLE (0) |
Constant TRX_OFF_AVDD_DISABLE for sub-register SR_TRX_OFF_AVDD_EN in register TRX_CTRL_2.
| #define TRX_OFF_AVDD_ENABLE (1) |
Constant TRX_OFF_AVDD_ENABLE for sub-register SR_TRX_OFF_AVDD_EN in register TRX_CTRL_2.
| #define TRX_OFF_TO_PLL_ON_TIME_US (170) |
Referenced by perform_cca_twice(), and switch_pll_on().
| #define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES (35) |
Referenced by set_trx_state().
| #define TRX_SUPPORTED_CHANNELS (0x000007FF) |
Parameter definitions.
Important parameters.
Referenced by apply_channel_page_configuration(), and tal_pib_set().
| #define TRX_SUPPORTED_CHANNELS_CHINA (0x0000000F) |
Referenced by apply_channel_page_configuration(), and tal_pib_set().
| #define TX_AUTO_CRC_DISABLE (0) |
Constant TX_AUTO_CRC_DISABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1.
| #define TX_AUTO_CRC_ENABLE (1) |
Constant TX_AUTO_CRC_ENABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1.
| #define TX_PWR_TOLERANCE (0x80) |
Referenced by limit_tx_pwr(), and set_default_tx_pwr().
| #define UPLD_RES_FT_DISABLE (0) |
Constant UPLD_RES_FT_DISABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1.
| #define UPLD_RES_FT_ENABLE (1) |
Constant UPLD_RES_FT_ENABLE for sub-register SR_AACK_UPLD_RES_FT in register XAH_CTRL_1.
| #define VERSION_NUM_AT86RF12B_C (0x03) |
Constant VERSION_NUM_AT86RF12B_C for sub-register SR_VERSION_NUM in register VERSION_NUM.
| typedef enum tal_trx_status_tag tal_trx_status_t |
sub-register TRX_STATUS in register TRX_STATUS
| typedef enum trx_cmd_tag trx_cmd_t |
Enumerations.
sub-register TRX_CMD in register TRX_STATE
| typedef enum trx_irq_reason_tag trx_irq_reason_t |
sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS
| typedef enum trx_trac_status_tag trx_trac_status_t |
sub-register TRAC_STATUS in register TRX_STATE
| enum tal_trx_status_tag |
sub-register TRX_STATUS in register TRX_STATUS
| Enumerator | |
|---|---|
| P_ON |
Constant P_ON for sub-register SR_TRX_STATUS. |
| BUSY_RX |
Constant BUSY_RX for sub-register SR_TRX_STATUS. |
| BUSY_TX |
Constant BUSY_TX for sub-register SR_TRX_STATUS. |
| RX_ON |
Constant RX_ON for sub-register SR_TRX_STATUS. |
| TRX_OFF |
Constant TRX_OFF for sub-register SR_TRX_STATUS. |
| PLL_ON |
Constant PLL_ON for sub-register SR_TRX_STATUS. |
| TRX_SLEEP |
Constant TRX_SLEEP for sub-register SR_TRX_STATUS. |
| BUSY_RX_AACK |
Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS. |
| BUSY_TX_ARET |
Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS. |
| RX_AACK_ON |
Constant RX_AACK_ON for sub-register SR_TRX_STATUS. |
| TX_ARET_ON |
Constant TX_ARET_ON for sub-register SR_TRX_STATUS. |
| RX_ON_NOCLK |
Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS. |
| RX_AACK_ON_NOCLK |
Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS. |
| BUSY_RX_AACK_NOCLK |
Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS. |
| STATE_TRANSITION_IN_PROGRESS |
Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS. |
| enum trx_cmd_tag |
Enumerations.
sub-register TRX_CMD in register TRX_STATE
| Enumerator | |
|---|---|
| CMD_NOP |
Constant CMD_NOP for sub-register SR_TRX_CMD. |
| CMD_TX_START |
Constant CMD_TX_START for sub-register SR_TRX_CMD. |
| CMD_FORCE_TRX_OFF |
Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD. |
| CMD_FORCE_PLL_ON |
Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD. |
| CMD_RX_ON |
Constant CMD_RX_ON for sub-register SR_TRX_CMD. |
| CMD_TRX_OFF |
Constant CMD_TRX_OFF for sub-register SR_TRX_CMD. |
| CMD_PLL_ON |
Constant CMD_PLL_ON for sub-register SR_TRX_CMD. |
| CMD_RX_AACK_ON |
Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD. |
| CMD_TX_ARET_ON |
Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD. |
| CMD_SLEEP |
Software implemented command. |
| enum trx_irq_reason_tag |
sub-register IRQ_7_BAT_LOW IRQ_6_TRX_UR IRQ_5_AMI IRQ_4_CCA_ED_DONE IRQ_3_TRX_END IRQ_2_RX_START IRQ_1_PLL_UNLOCK IRQ_0_PLL_LOCK in register IRQ_STATUS
| Enumerator | |
|---|---|
| TRX_IRQ_7_BAT_LOW |
Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW. |
| TRX_IRQ_6_TRX_UR |
Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR. |
| TRX_IRQ_5_AMI |
Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI. |
| TRX_IRQ_4_CCA_ED_DONE |
Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE. |
| TRX_IRQ_3_TRX_END |
Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END. |
| TRX_IRQ_2_RX_START |
Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START. |
| TRX_IRQ_1_PLL_UNLOCK |
Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK. |
| TRX_IRQ_0_PLL_LOCK |
Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK. |
| TRX_NO_IRQ |
No interrupt is indicated by IRQ_STATUS register. |
| enum trx_trac_status_tag |
sub-register TRAC_STATUS in register TRX_STATE
| Enumerator | |
|---|---|
| TRAC_SUCCESS |
Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS. |
| TRAC_SUCCESS_DATA_PENDING |
Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS. |
| TRAC_SUCCESS_WAIT_FOR_ACK |
Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS. |
| TRAC_CHANNEL_ACCESS_FAILURE |
Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS. |
| TRAC_NO_ACK |
Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS. |
| TRAC_INVALID |
Constant TRAC_INVALID for sub-register SR_TRAC_STATUS. |
1.8.5