AT86RF212B PHY Layer

The AT86RF212 is a low-power ,low voltage 700/800/900 MHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate sub 1GHz ISM band applications.

Macros
#define	AACK_ACK_TIME   2
#define	AACK_DIS_ACK   4
#define	AACK_FLTR_RES_FT   5
#define	AACK_FVN_MODE   6
#define	AACK_I_AM_COORD   3
#define	AACK_PROM_MODE   1
#define	AACK_SET_PD   5
#define	AACK_UPLD_RES_FT   4
#define	AES_BLOCK_SIZE   16
#define	AES_CORE_CYCLE_TIME   24 /* us */
#define	AES_CTRL_DIR   3
#define	AES_CTRL_M_REG   0x94
#define	AES_CTRL_MODE   4
#define	AES_CTRL_REG   0x83
#define	AES_CTRL_REQUEST   7
#define	AES_KEY_REG   0x84
#define	AES_STATE_REG   0x84
#define	AES_STATUS_DONE   0
#define	AES_STATUS_ER   7
#define	AES_STATUS_REG   0x82
#define	ALT_SPECTRUM   4 /* Only in AT86RF212B */
#define	AMI   5
#define	ANT_CTRL   0
#define	ANT_DIV_EN   3 /* Only in AT86RF212B */
#define	ANT_DIV_REG   0x0d
#define	ANT_EXT_SW_EN   2
#define	ANT_SEL   7 /* Only in AT86RF212B */
#define	AVDD_OK   6
#define	AVREG_EXT   7
#define	BAT_LOW   7
#define	BATMON_HR   4
#define	BATMON_OK   5
#define	BATMON_REG   0x11
#define	BATMON_VTH   0
#define	BPSK_OQPSK   3
#define	CC_BAND   0
#define	CC_CTRL_0_REG   0x13
#define	CC_CTRL_1_REG   0x14
#define	CCA_CS_THRES   4 /* Only in AT86RF212B */
#define	CCA_DONE   7
#define	CCA_ED_DONE   4
#define	CCA_ED_THRES   0
#define	CCA_MODE   5
#define	CCA_REQUEST   7
#define	CCA_STATUS   6
#define	CCA_THRES_REG   0x09
#define	CHANNEL   0
#define	CLKM_CTRL   0
#define	CLKM_SHA_SEL   3
#define	CSMA_BE_REG   0x2f
#define	CSMA_LBT_MODE   6
#define	CSMA_SEED_0_REG   0x2d
#define	CSMA_SEED_1   0
#define	CSMA_SEED_1_REG   0x2e
#define	DVDD_OK   2
#define	DVREG_EXT   3
#define	F_SHIFT_MODE   2 /* Only in AT86RF212B */
#define	FTN_CTRL_REG   0x18
#define	FTN_START   7
#define	GC_PA   5
#define	GC_TX_OFFS   0
#define	IEEE_ADDR_0_REG   0x24
#define	IEEE_ADDR_1_REG   0x25
#define	IEEE_ADDR_2_REG   0x26
#define	IEEE_ADDR_3_REG   0x27
#define	IEEE_ADDR_4_REG   0x28
#define	IEEE_ADDR_5_REG   0x29
#define	IEEE_ADDR_6_REG   0x2a
#define	IEEE_ADDR_7_REG   0x2b
#define	IRQ_2_EXT_EN   6
#define	IRQ_MASK_MODE   1
#define	IRQ_MASK_REG   0x0e
#define	IRQ_POLARITY   0
#define	IRQ_STATUS_REG   0x0f
#define	JCM_EN   5
#define	MAN_ID_0_REG   0x1e
#define	MAN_ID_1_REG   0x1f
#define	MAX_BE   4
#define	MAX_CSMA_RETRES   1
#define	MAX_FRAME_RETRES   4
#define	MIN_BE   0
#define	OQPSK_DATA_RATE   0
#define	OQPSK_SCRAM_EN   5
#define	OQPSK_SUB1_RC_EN   4 /* Only in AT86RF212 */
#define	PA_BOOST   7
#define	PA_EXT_EN   7
#define	PA_LT   6
#define	PAD_IO   6
#define	PAD_IO_CLKM   4
#define	PAN_ID_0_REG   0x22
#define	PAN_ID_1_REG   0x23
#define	PART_NUM_REG   0x1c
#define	PHY_CC_CCA_REG   0x08
#define	PHY_ED_LEVEL_REG   0x07
#define	PHY_RSSI_REG   0x06
#define	PHY_TX_PWR_REG   0x05
#define	PLL_CF   0 /* Only in AT86RF212 */
#define	PLL_CF_REG   0x1a
#define	PLL_CF_START   7
#define	PLL_DCU_REG   0x1b
#define	PLL_DCU_START   7
#define	PLL_LOCK   0
#define	PLL_LOCK_CP   7
#define	PLL_UNLOCK   1
#define	RANDOM_NUMBER_UPDATE_INTERVAL   1 /* us */
#define	RF_CMD_FRAME_R   ((0 << 7) | (0 << 6) | (1 << 5))
#define	RF_CMD_FRAME_W   ((0 << 7) | (1 << 6) | (1 << 5))
#define	RF_CMD_REG_R   ((1 << 7) | (0 << 6))
#define	RF_CMD_REG_W   ((1 << 7) | (1 << 6))
#define	RF_CMD_SRAM_R   ((0 << 7) | (0 << 6) | (0 << 5))
#define	RF_CMD_SRAM_W   ((0 << 7) | (1 << 6) | (0 << 5))
#define	RF_CTRL_0_REG   0x16
#define	RF_CTRL_1_REG   0x19 /* Only in AT86RF212 */
#define	RF_MC   4 /* Only in AT86RF212 */
#define	RND_VALUE   5
#define	RSSI   0
#define	RX_BL_CTRL   4
#define	RX_CRC_VALID   7
#define	RX_CTRL_REG   0x0a
#define	RX_OVERRIDE   4 /* Only in AT86RF212B */
#define	RX_PDT_DIS   7
#define	RX_PDT_LEVEL   0
#define	RX_SAFE_MODE   7
#define	RX_START   2
#define	RX_SYN_REG   0x15
#define	SFD_VALUE_REG   0x0b
#define	SHORT_ADDR_0_REG   0x20
#define	SHORT_ADDR_1_REG   0x21
#define	SLOTTED_OPERATION   0
#define	SPI_CMD_MODE   2
#define	SUB_MODE   2
#define	TRAC_STATUS   5
#define	TRAC_STATUS_CHANNEL_ACCESS_FAILURE   3
#define	TRAC_STATUS_INVALID   7
#define	TRAC_STATUS_NO_ACK   5
#define	TRAC_STATUS_SUCCESS   0
#define	TRAC_STATUS_SUCCESS_DATA_PENDING   1
#define	TRAC_STATUS_SUCCESS_WAIT_FOR_ACK   2
#define	TRX_CMD   0
#define	TRX_CMD_FORCE_PLL_ON   4
#define	TRX_CMD_FORCE_TRX_OFF   3
#define	TRX_CMD_NOP   0
#define	TRX_CMD_PLL_ON   9
#define	TRX_CMD_RX_AACK_ON   22
#define	TRX_CMD_RX_ON   6
#define	TRX_CMD_TRX_OFF   8
#define	TRX_CMD_TX_ARET_ON   25
#define	TRX_CMD_TX_START   2
#define	TRX_CTRL_0_REG   0x03
#define	TRX_CTRL_1_REG   0x04
#define	TRX_CTRL_2_REG   0x0c
#define	TRX_END   3
#define	TRX_OFF_AVDD_EN   6
#define	TRX_STATE_REG   0x02
#define	TRX_STATUS   0
#define	TRX_STATUS_BUSY_RX   1
#define	TRX_STATUS_BUSY_RX_AACK   17
#define	TRX_STATUS_BUSY_RX_AACK_NOCLK   30
#define	TRX_STATUS_BUSY_TX   2
#define	TRX_STATUS_BUSY_TX_ARET   18
#define	TRX_STATUS_MASK   0x1f
#define	TRX_STATUS_P_ON   0
#define	TRX_STATUS_PLL_ON   9
#define	TRX_STATUS_REG   0x01
#define	TRX_STATUS_RX_AACK_ON   22
#define	TRX_STATUS_RX_AACK_ON_NOCLK   29
#define	TRX_STATUS_RX_ON   6
#define	TRX_STATUS_RX_ON_NOCLK   28
#define	TRX_STATUS_SLEEP   15
#define	TRX_STATUS_STATE_TRANSITION   31
#define	TRX_STATUS_TRX_OFF   8
#define	TRX_STATUS_TX_ARET_ON   25
#define	TRX_UR   6
#define	TX_AUTO_CRC_ON   5
#define	TX_PWR   0
#define	VERSION_NUM_REG   0x1d
#define	VREG_CTRL_REG   0x10
#define	XAH_CTRL_0_REG   0x2c
#define	XAH_CTRL_1_REG   0x17
#define	XOSC_CTRL_REG   0x12
#define	XTAL_MODE   4
#define	XTAL_TRIM   0

#define AACK_ACK_TIME   2

#define AACK_DIS_ACK   4

#define AACK_FLTR_RES_FT   5

#define AACK_FVN_MODE   6

#define AACK_I_AM_COORD   3

#define AACK_PROM_MODE   1

#define AACK_SET_PD   5

#define AACK_UPLD_RES_FT   4

#define AES_BLOCK_SIZE   16

#define AES_CORE_CYCLE_TIME   24 /* us */

#define AES_CTRL_DIR   3

#define AES_CTRL_M_REG   0x94

#define AES_CTRL_MODE   4

#define AES_CTRL_REG   0x83

#define AES_CTRL_REQUEST   7

#define AES_KEY_REG   0x84

#define AES_STATE_REG   0x84

#define AES_STATUS_DONE   0

#define AES_STATUS_ER   7

#define AES_STATUS_REG   0x82

#define ALT_SPECTRUM   4 /* Only in AT86RF212B */

#define AMI   5

#define ANT_CTRL   0

#define ANT_DIV_EN   3 /* Only in AT86RF212B */

#define ANT_DIV_REG   0x0d

#define ANT_EXT_SW_EN   2

#define ANT_SEL   7 /* Only in AT86RF212B */

#define AVDD_OK   6

#define AVREG_EXT   7

#define BAT_LOW   7

#define BATMON_HR   4

#define BATMON_OK   5

#define BATMON_REG   0x11

#define BATMON_VTH   0

#define BPSK_OQPSK   3

Referenced by phyRssiBaseVal().

#define CC_BAND   0

#define CC_CTRL_0_REG   0x13

Referenced by phySetChannel().

#define CC_CTRL_1_REG   0x14

Referenced by phySetChannel().

#define CCA_CS_THRES   4 /* Only in AT86RF212B */

#define CCA_DONE   7

#define CCA_ED_DONE   4

#define CCA_ED_THRES   0

#define CCA_MODE   5

#define CCA_REQUEST   7

#define CCA_STATUS   6

#define CCA_THRES_REG   0x09

#define CHANNEL   0

#define CLKM_CTRL   0

#define CLKM_SHA_SEL   3

#define CSMA_BE_REG   0x2f

#define CSMA_LBT_MODE   6

#define CSMA_SEED_0_REG   0x2d

Referenced by PHY_SetShortAddr().

#define CSMA_SEED_1   0

#define CSMA_SEED_1_REG   0x2e

#define DVDD_OK   2

#define DVREG_EXT   3

#define F_SHIFT_MODE   2 /* Only in AT86RF212B */

#define FTN_CTRL_REG   0x18

#define FTN_START   7

#define GC_PA   5

#define GC_TX_OFFS   0

#define IEEE_ADDR_0_REG   0x24

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_1_REG   0x25

#define IEEE_ADDR_2_REG   0x26

#define IEEE_ADDR_3_REG   0x27

#define IEEE_ADDR_4_REG   0x28

#define IEEE_ADDR_5_REG   0x29

#define IEEE_ADDR_6_REG   0x2a

#define IEEE_ADDR_7_REG   0x2b

#define IRQ_2_EXT_EN   6

#define IRQ_MASK_MODE   1

Referenced by PHY_Init().

#define IRQ_MASK_REG   0x0e

#define IRQ_POLARITY   0

#define IRQ_STATUS_REG   0x0f

Referenced by PHY_DataReq(), PHY_TaskHandler(), and phySetRxState().

#define JCM_EN   5

#define MAN_ID_0_REG   0x1e

#define MAN_ID_1_REG   0x1f

#define MAX_BE   4

#define MAX_CSMA_RETRES   1

#define MAX_FRAME_RETRES   4

#define MIN_BE   0

#define OQPSK_DATA_RATE   0

#define OQPSK_SCRAM_EN   5

#define OQPSK_SUB1_RC_EN   4 /* Only in AT86RF212 */

#define PA_BOOST   7

#define PA_EXT_EN   7

#define PA_LT   6

#define PAD_IO   6

#define PAD_IO_CLKM   4

#define PAN_ID_0_REG   0x22

Referenced by PHY_SetPanId().

#define PAN_ID_1_REG   0x23

Referenced by PHY_SetPanId().

#define PART_NUM_REG   0x1c

#define PHY_CC_CCA_REG   0x08

Referenced by phySetChannel().

#define PHY_ED_LEVEL_REG   0x07

Referenced by PHY_TaskHandler().

#define PHY_RSSI_REG   0x06

Referenced by PHY_RandomReq().

#define PHY_TX_PWR_REG   0x05

Referenced by PHY_Init().

#define PLL_CF   0 /* Only in AT86RF212 */

#define PLL_CF_REG   0x1a

#define PLL_CF_START   7

#define PLL_DCU_REG   0x1b

#define PLL_DCU_START   7

#define PLL_LOCK   0

#define PLL_LOCK_CP   7

#define PLL_UNLOCK   1

#define RANDOM_NUMBER_UPDATE_INTERVAL   1 /* us */

Referenced by PHY_RandomReq().

#define RF_CMD_FRAME_R   ((0 << 7) | (0 << 6) | (1 << 5))

#define RF_CMD_FRAME_W   ((0 << 7) | (1 << 6) | (1 << 5))

#define RF_CMD_REG_R   ((1 << 7) | (0 << 6))

#define RF_CMD_REG_W   ((1 << 7) | (1 << 6))

#define RF_CMD_SRAM_R   ((0 << 7) | (0 << 6) | (0 << 5))

#define RF_CMD_SRAM_W   ((0 << 7) | (1 << 6) | (0 << 5))

#define RF_CTRL_0_REG   0x16

Referenced by PHY_Init().

#define RF_CTRL_1_REG   0x19 /* Only in AT86RF212 */

#define RF_MC   4 /* Only in AT86RF212 */

#define RND_VALUE   5

Referenced by PHY_RandomReq().

#define RSSI   0

#define RX_BL_CTRL   4

#define RX_CRC_VALID   7

#define RX_CTRL_REG   0x0a

#define RX_OVERRIDE   4 /* Only in AT86RF212B */

#define RX_PDT_DIS   7

#define RX_PDT_LEVEL   0

#define RX_SAFE_MODE   7

Referenced by PHY_Init().

#define RX_START   2

#define RX_SYN_REG   0x15

#define SFD_VALUE_REG   0x0b

#define SHORT_ADDR_0_REG   0x20

Referenced by PHY_SetShortAddr().

#define SHORT_ADDR_1_REG   0x21

Referenced by PHY_SetShortAddr().

#define SLOTTED_OPERATION   0

#define SPI_CMD_MODE   2

Referenced by PHY_Init().

#define SUB_MODE   2

Referenced by phyRssiBaseVal().

#define TRAC_STATUS   5

Referenced by PHY_TaskHandler().

#define TRAC_STATUS_CHANNEL_ACCESS_FAILURE   3

Referenced by PHY_TaskHandler().

#define TRAC_STATUS_INVALID   7

#define TRAC_STATUS_NO_ACK   5

Referenced by PHY_TaskHandler().

#define TRAC_STATUS_SUCCESS   0

Referenced by PHY_TaskHandler().

#define TRAC_STATUS_SUCCESS_DATA_PENDING   1

#define TRAC_STATUS_SUCCESS_WAIT_FOR_ACK   2

#define TRX_CMD   0

#define TRX_CMD_FORCE_PLL_ON   4

#define TRX_CMD_FORCE_TRX_OFF   3

Referenced by phyTrxSetState().

#define TRX_CMD_NOP   0

#define TRX_CMD_PLL_ON   9

#define TRX_CMD_RX_AACK_ON   22

Referenced by phySetRxState().

#define TRX_CMD_RX_ON   6

Referenced by PHY_RandomReq().

#define TRX_CMD_TRX_OFF   8

Referenced by PHY_Init(), PHY_Sleep(), and phySetRxState().

#define TRX_CMD_TX_ARET_ON   25

Referenced by PHY_DataReq().

#define TRX_CMD_TX_START   2

#define TRX_CTRL_0_REG   0x03

#define TRX_CTRL_1_REG   0x04

Referenced by PHY_Init().

#define TRX_CTRL_2_REG   0x0c

Referenced by PHY_Init(), and phySetChannel().

#define TRX_END   3

Referenced by PHY_TaskHandler().

#define TRX_OFF_AVDD_EN   6

#define TRX_STATE_REG   0x02

Referenced by PHY_Init(), PHY_TaskHandler(), and phyTrxSetState().

#define TRX_STATUS   0

#define TRX_STATUS_BUSY_RX   1

#define TRX_STATUS_BUSY_RX_AACK   17

#define TRX_STATUS_BUSY_RX_AACK_NOCLK   30

#define TRX_STATUS_BUSY_TX   2

#define TRX_STATUS_BUSY_TX_ARET   18

#define TRX_STATUS_MASK   0x1f

Referenced by PHY_Init(), phyTrxSetState(), and phyWaitState().

#define TRX_STATUS_P_ON   0

#define TRX_STATUS_PLL_ON   9

#define TRX_STATUS_REG   0x01

Referenced by PHY_Init(), phyTrxSetState(), and phyWaitState().

#define TRX_STATUS_RX_AACK_ON   22

Referenced by PHY_TaskHandler().

#define TRX_STATUS_RX_AACK_ON_NOCLK   29

#define TRX_STATUS_RX_ON   6

#define TRX_STATUS_RX_ON_NOCLK   28

#define TRX_STATUS_SLEEP   15

#define TRX_STATUS_STATE_TRANSITION   31

#define TRX_STATUS_TRX_OFF   8

Referenced by PHY_Init(), and phyTrxSetState().

#define TRX_STATUS_TX_ARET_ON   25

#define TRX_UR   6

#define TX_AUTO_CRC_ON   5

Referenced by PHY_Init().

#define TX_PWR   0

#define VERSION_NUM_REG   0x1d

#define VREG_CTRL_REG   0x10

#define XAH_CTRL_0_REG   0x2c

#define XAH_CTRL_1_REG   0x17

#define XOSC_CTRL_REG   0x12

#define XTAL_MODE   4

#define XTAL_TRIM   0