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Data Structures | Macros | Enumerations
ATMEGARFA1 PHY Layer
PHY

The ATmega128RFA1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4 GHz ISM band.

It is derived from the ATmega1281 microcontroller and the AT86RF231 radio transceiver. Refer ATMEGARFA1 Data Sheet for detailed information .

Data Structures

struct  __struct_ANT_DIV_REG
 
struct  __struct_BATMON_REG
 
struct  __struct_CCA_THRES_REG
 
struct  __struct_CSMA_BE_REG
 
struct  __struct_CSMA_SEED_1_REG
 
struct  __struct_FTN_CTRL_REG
 
struct  __struct_IRQ_MASK_REG
 
struct  __struct_IRQ_STATUS_REG
 
struct  __struct_PHY_CC_CCA_REG
 
struct  __struct_PHY_RSSI_REG
 
struct  __struct_PHY_TX_PWR_REG
 
struct  __struct_PLL_CF_REG
 
struct  __struct_PLL_DCU_REG
 
struct  __struct_RX_CTRL_REG
 
struct  __struct_RX_SYN_REG
 
struct  __struct_TRX_CTRL_1_REG
 
struct  __struct_TRX_CTRL_2_REG
 
struct  __struct_TRX_STATE_REG
 
struct  __struct_TRX_STATUS_REG
 
struct  __struct_TRXPR_REG
 
struct  __struct_VREG_CTRL_REG
 
struct  __struct_XAH_CTRL_0_REG
 
struct  __struct_XAH_CTRL_1_REG
 
struct  __struct_XOSC_CTRL_REG
 

Macros

#define AES_BLOCK_SIZE   16
 
#define AES_CTRL_DIR   3
 
#define AES_CTRL_IM   2
 
#define AES_CTRL_MODE   5
 
#define AES_CTRL_REQUEST   7
 
#define AES_STATUS_ER   7
 
#define AES_STATUS_RY   0
 
#define ANT_DIV_REG   MMIO_REG(0x14D, uint8_t)
 
#define ANT_DIV_REG_s   MMIO_REG(0x14D, struct __struct_ANT_DIV_REG)
 
#define BATMON_REG   MMIO_REG(0x151, uint8_t)
 
#define BATMON_REG_s   MMIO_REG(0x151, struct __struct_BATMON_REG)
 
#define CCA_THRES_REG   MMIO_REG(0x149, uint8_t)
 
#define CCA_THRES_REG_s   MMIO_REG(0x149, struct __struct_CCA_THRES_REG)
 
#define CSMA_BE_REG   MMIO_REG(0x16F, uint8_t)
 
#define CSMA_BE_REG_s   MMIO_REG(0x16F, struct __struct_CSMA_BE_REG)
 
#define CSMA_SEED_0_REG   MMIO_REG(0x16D, uint8_t)
 
#define CSMA_SEED_1_REG   MMIO_REG(0x16E, uint8_t)
 
#define CSMA_SEED_1_REG_s   MMIO_REG(0x16E, struct __struct_CSMA_SEED_1_REG)
 
#define FTN_CTRL_REG   MMIO_REG(0x158, uint8_t)
 
#define FTN_CTRL_REG_s   MMIO_REG(0x158, struct __struct_FTN_CTRL_REG)
 
#define IEEE_ADDR_0_REG   MMIO_REG(0x164, uint8_t)
 
#define IEEE_ADDR_1_REG   MMIO_REG(0x165, uint8_t)
 
#define IEEE_ADDR_2_REG   MMIO_REG(0x166, uint8_t)
 
#define IEEE_ADDR_3_REG   MMIO_REG(0x167, uint8_t)
 
#define IEEE_ADDR_4_REG   MMIO_REG(0x168, uint8_t)
 
#define IEEE_ADDR_5_REG   MMIO_REG(0x169, uint8_t)
 
#define IEEE_ADDR_6_REG   MMIO_REG(0x16A, uint8_t)
 
#define IEEE_ADDR_7_REG   MMIO_REG(0x16B, uint8_t)
 
#define IRQ_MASK_REG   MMIO_REG(0x14E, uint8_t)
 
#define IRQ_MASK_REG_s   MMIO_REG(0x14E, struct __struct_IRQ_MASK_REG)
 
#define IRQ_STATUS_CLEAR_VALUE   0xff
 
#define IRQ_STATUS_REG   MMIO_REG(0x14F, uint8_t)
 
#define IRQ_STATUS_REG_s   MMIO_REG(0x14F, struct __struct_IRQ_STATUS_REG)
 
#define MAN_ID_0_REG   MMIO_REG(0x15E, uint8_t)
 
#define MAN_ID_1_REG   MMIO_REG(0x15F, uint8_t)
 
#define MMIO_REG(mem_addr, type)   (*(volatile type *)(mem_addr))
 
#define PAN_ID_0_REG   MMIO_REG(0x162, uint8_t)
 
#define PAN_ID_1_REG   MMIO_REG(0x163, uint8_t)
 
#define PART_NUM_REG   MMIO_REG(0x15C, uint8_t)
 
#define PHY_CC_CCA_REG   MMIO_REG(0x148, uint8_t)
 
#define PHY_CC_CCA_REG_s   MMIO_REG(0x148, struct __struct_PHY_CC_CCA_REG)
 
#define PHY_ED_LEVEL_REG   MMIO_REG(0x147, uint8_t)
 
#define PHY_RSSI_REG   MMIO_REG(0x146, uint8_t)
 
#define PHY_RSSI_REG_s   MMIO_REG(0x146, struct __struct_PHY_RSSI_REG)
 
#define PHY_TX_PWR_REG   MMIO_REG(0x145, uint8_t)
 
#define PHY_TX_PWR_REG_s   MMIO_REG(0x145, struct __struct_PHY_TX_PWR_REG)
 
#define PLL_CF_REG   MMIO_REG(0x15A, uint8_t)
 
#define PLL_CF_REG_s   MMIO_REG(0x15A, struct __struct_PLL_CF_REG)
 
#define PLL_DCU_REG   MMIO_REG(0x15B, uint8_t)
 
#define PLL_DCU_REG_s   MMIO_REG(0x15B, struct __struct_PLL_DCU_REG)
 
#define RANDOM_NUMBER_UPDATE_INTERVAL   1 /* us */
 
#define RX_CTRL_REG   MMIO_REG(0x14A, uint8_t)
 
#define RX_CTRL_REG_s   MMIO_REG(0x14A, struct __struct_RX_CTRL_REG)
 
#define RX_SYN_REG   MMIO_REG(0x155, uint8_t)
 
#define RX_SYN_REG_s   MMIO_REG(0x155, struct __struct_RX_SYN_REG)
 
#define SFD_VALUE_REG   MMIO_REG(0x14B, uint8_t)
 
#define SHORT_ADDR_0_REG   MMIO_REG(0x160, uint8_t)
 
#define SHORT_ADDR_1_REG   MMIO_REG(0x161, uint8_t)
 
#define TRX_CTRL_1_REG   MMIO_REG(0x144, uint8_t)
 
#define TRX_CTRL_1_REG_s   MMIO_REG(0x144, struct __struct_TRX_CTRL_1_REG)
 
#define TRX_CTRL_2_REG   MMIO_REG(0x14C, uint8_t)
 
#define TRX_CTRL_2_REG_s   MMIO_REG(0x14C, struct __struct_TRX_CTRL_2_REG)
 
#define TRX_FRAME_BUFFER(index)   MMIO_REG(0x180 + (index), uint8_t)
 
#define TRX_STATE_REG   MMIO_REG(0x142, uint8_t)
 
#define TRX_STATE_REG_s   MMIO_REG(0x142, struct __struct_TRX_STATE_REG)
 
#define TRX_STATUS_REG   MMIO_REG(0x141, uint8_t)
 
#define TRX_STATUS_REG_s   MMIO_REG(0x141, struct __struct_TRX_STATUS_REG)
 
#define TRXPR_REG   MMIO_REG(0x139, uint8_t)
 
#define TRXPR_REG_s   MMIO_REG(0x139, struct __struct_TRXPR_REG)
 
#define TST_CTRL_DIGI_REG   MMIO_REG(0x176, uint8_t)
 
#define TST_RX_LENGTH_REG   MMIO_REG(0x17B, uint8_t)
 
#define VERSION_NUM_REG   MMIO_REG(0x15D, uint8_t)
 
#define VREG_CTRL_REG   MMIO_REG(0x150, uint8_t)
 
#define VREG_CTRL_REG_s   MMIO_REG(0x150, struct __struct_VREG_CTRL_REG)
 
#define XAH_CTRL_0_REG   MMIO_REG(0x16C, uint8_t)
 
#define XAH_CTRL_0_REG_s   MMIO_REG(0x16C, struct __struct_XAH_CTRL_0_REG)
 
#define XAH_CTRL_1_REG   MMIO_REG(0x157, uint8_t)
 
#define XAH_CTRL_1_REG_s   MMIO_REG(0x157, struct __struct_XAH_CTRL_1_REG)
 
#define XOSC_CTRL_REG   MMIO_REG(0x152, uint8_t)
 
#define XOSC_CTRL_REG_s   MMIO_REG(0x152, struct __struct_XOSC_CTRL_REG)
 

Enumerations

enum  {
  TRX_STATUS_P_ON = 0,
  TRX_STATUS_BUSY_RX = 1,
  TRX_STATUS_BUSY_TX = 2,
  TRX_STATUS_RX_ON = 6,
  TRX_STATUS_TRX_OFF = 8,
  TRX_STATUS_PLL_ON = 9,
  TRX_STATUS_SLEEP = 15,
  TRX_STATUS_BUSY_RX_AACK = 17,
  TRX_STATUS_BUSY_TX_ARET = 18,
  TRX_STATUS_RX_AACK_ON = 22,
  TRX_STATUS_TX_ARET_ON = 25,
  TRX_STATUS_RX_ON_NOCLK = 28,
  TRX_STATUS_RX_AACK_ON_NOCLK = 29,
  TRX_STATUS_BUSY_RX_AACK_NOCLK = 30,
  TRX_STATUS_STATE_TRANSITION_IN_PROGRESS = 31
}
 
enum  {
  TRX_CMD_NOP = 0,
  TRX_CMD_TX_START = 2,
  TRX_CMD_FORCE_TRX_OFF = 3,
  TRX_CMD_FORCE_PLL_ON = 4,
  TRX_CMD_RX_ON = 6,
  TRX_CMD_TRX_OFF = 8,
  TRX_CMD_PLL_ON = 9,
  TRX_CMD_RX_AACK_ON = 22,
  TRX_CMD_TX_ARET_ON = 25
}
 
enum  {
  TRAC_STATUS_SUCCESS = 0,
  TRAC_STATUS_SUCCESS_DATA_PENDING = 1,
  TRAC_STATUS_SUCCESS_WAIT_FOR_ACK = 2,
  TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3,
  TRAC_STATUS_NO_ACK = 5,
  TRAC_STATUS_INVALID = 7
}
 
enum  {
  TX_PWR_3_5_DBM = 0x00,
  TX_PWR_3_3_DBM = 0x01,
  TX_PWR_2_8_DBM = 0x02,
  TX_PWR_2_3_DBM = 0x03,
  TX_PWR_1_8_DBM = 0x04,
  TX_PWR_1_2_DBM = 0x05,
  TX_PWR_0_5_DBM = 0x06,
  TX_PWR_MIN_0_5_DBM = 0x07,
  TX_PWR_MIN_1_5_DBM = 0x08,
  TX_PWR_MIN_2_5_DBM = 0x09,
  TX_PWR_MIN_3_5_DBM = 0x0A,
  TX_PWR_MIN_4_5_DBM = 0x0B,
  TX_PWR_MIN_6_5_DBM = 0x0C,
  TX_PWR_MIN_8_5_DBM = 0x0D,
  TX_PWR_MIN_11_5_DBM = 0x0E,
  TX_PWR_MIN_16_5_DBM = 0x0F
}
 
enum  {
  TX_PWR_PA_LT_2US = 0,
  TX_PWR_PA_LT_4US = 1,
  TX_PWR_PA_LT_6US = 2,
  TX_PWR_PA_LT_8US = 3
}
 
enum  {
  TX_PWR_PA_BUF_LT_0US = 0,
  TX_PWR_PA_BUF_LT_2US = 1,
  TX_PWR_PA_BUF_LT_4US = 2,
  TX_PWR_PA_BUF_LT_6US = 3
}
 
enum  {
  PHY_STATUS_SUCCESS = 0,
  PHY_STATUS_CHANNEL_ACCESS_FAILURE = 1,
  PHY_STATUS_NO_ACK = 2,
  PHY_STATUS_ERROR = 3
}
 
#define PHY_RSSI_BASE_VAL   (-90)
 
#define PHY_HAS_RANDOM_NUMBER_GENERATOR
 
#define PHY_HAS_AES_MODULE
 
typedef struct PHY_DataInd_t PHY_DataInd_t
 
void PHY_Init (void)
 
void PHY_SetRxState (bool rx)
 
void PHY_SetChannel (uint8_t channel)
 
void PHY_SetPanId (uint16_t panId)
 
void PHY_SetShortAddr (uint16_t addr)
 
void PHY_SetTxPower (uint8_t txPower)
 
void PHY_Sleep (void)
 
void PHY_Wakeup (void)
 
void PHY_DataReq (uint8_t *data)
 
void PHY_DataConf (uint8_t status)
 
void PHY_DataInd (PHY_DataInd_t *ind)
 
void PHY_TaskHandler (void)
 
void PHY_SetIEEEAddr (uint8_t *ieee_addr)
 
uint16_t PHY_RandomReq (void)
 
void PHY_EncryptReq (uint8_t *text, uint8_t *key)
 
int8_t PHY_EdReq (void)
 

#define AES_BLOCK_SIZE   16
#define AES_CTRL_DIR   3
#define AES_CTRL_IM   2
#define AES_CTRL_MODE   5
#define AES_CTRL_REQUEST   7
#define AES_STATUS_ER   7
#define AES_STATUS_RY   0
#define ANT_DIV_REG   MMIO_REG(0x14D, uint8_t)
#define ANT_DIV_REG_s   MMIO_REG(0x14D, struct __struct_ANT_DIV_REG)
#define BATMON_REG   MMIO_REG(0x151, uint8_t)
#define BATMON_REG_s   MMIO_REG(0x151, struct __struct_BATMON_REG)
#define CCA_THRES_REG   MMIO_REG(0x149, uint8_t)
#define CCA_THRES_REG_s   MMIO_REG(0x149, struct __struct_CCA_THRES_REG)
#define CSMA_BE_REG   MMIO_REG(0x16F, uint8_t)
#define CSMA_BE_REG_s   MMIO_REG(0x16F, struct __struct_CSMA_BE_REG)
#define CSMA_SEED_0_REG   MMIO_REG(0x16D, uint8_t)

Referenced by PHY_Init(), and PHY_SetShortAddr().

#define CSMA_SEED_1_REG   MMIO_REG(0x16E, uint8_t)
#define CSMA_SEED_1_REG_s   MMIO_REG(0x16E, struct __struct_CSMA_SEED_1_REG)
#define FTN_CTRL_REG   MMIO_REG(0x158, uint8_t)
#define FTN_CTRL_REG_s   MMIO_REG(0x158, struct __struct_FTN_CTRL_REG)
#define IEEE_ADDR_0_REG   MMIO_REG(0x164, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_1_REG   MMIO_REG(0x165, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_2_REG   MMIO_REG(0x166, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_3_REG   MMIO_REG(0x167, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_4_REG   MMIO_REG(0x168, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_5_REG   MMIO_REG(0x169, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_6_REG   MMIO_REG(0x16A, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_7_REG   MMIO_REG(0x16B, uint8_t)

Referenced by PHY_SetIEEEAddr().

#define IRQ_MASK_REG   MMIO_REG(0x14E, uint8_t)
#define IRQ_MASK_REG_s   MMIO_REG(0x14E, struct __struct_IRQ_MASK_REG)
#define IRQ_STATUS_CLEAR_VALUE   0xff
#define IRQ_STATUS_REG   MMIO_REG(0x14F, uint8_t)

Referenced by PHY_DataReq(), and phySetRxState().

#define IRQ_STATUS_REG_s   MMIO_REG(0x14F, struct __struct_IRQ_STATUS_REG)

Referenced by PHY_EdReq(), and PHY_TaskHandler().

#define MAN_ID_0_REG   MMIO_REG(0x15E, uint8_t)
#define MAN_ID_1_REG   MMIO_REG(0x15F, uint8_t)
#define MMIO_REG (   mem_addr,
  type 
)    (*(volatile type *)(mem_addr))
#define PAN_ID_0_REG   MMIO_REG(0x162, uint8_t)

Referenced by PHY_SetPanId().

#define PAN_ID_1_REG   MMIO_REG(0x163, uint8_t)

Referenced by PHY_SetPanId().

#define PART_NUM_REG   MMIO_REG(0x15C, uint8_t)
#define PHY_CC_CCA_REG   MMIO_REG(0x148, uint8_t)
#define PHY_CC_CCA_REG_s   MMIO_REG(0x148, struct __struct_PHY_CC_CCA_REG)

Referenced by PHY_SetChannel().

#define PHY_ED_LEVEL_REG   MMIO_REG(0x147, uint8_t)

Referenced by PHY_EdReq(), and PHY_TaskHandler().

#define PHY_HAS_AES_MODULE
#define PHY_HAS_RANDOM_NUMBER_GENERATOR
#define PHY_RSSI_BASE_VAL   (-90)

Referenced by PHY_EdReq(), and PHY_TaskHandler().

#define PHY_RSSI_REG   MMIO_REG(0x146, uint8_t)
#define PHY_RSSI_REG_s   MMIO_REG(0x146, struct __struct_PHY_RSSI_REG)

Referenced by PHY_RandomReq().

#define PHY_TX_PWR_REG   MMIO_REG(0x145, uint8_t)
#define PHY_TX_PWR_REG_s   MMIO_REG(0x145, struct __struct_PHY_TX_PWR_REG)

Referenced by PHY_SetTxPower().

#define PLL_CF_REG   MMIO_REG(0x15A, uint8_t)
#define PLL_CF_REG_s   MMIO_REG(0x15A, struct __struct_PLL_CF_REG)
#define PLL_DCU_REG   MMIO_REG(0x15B, uint8_t)
#define PLL_DCU_REG_s   MMIO_REG(0x15B, struct __struct_PLL_DCU_REG)
#define RANDOM_NUMBER_UPDATE_INTERVAL   1 /* us */

Referenced by PHY_RandomReq().

#define RX_CTRL_REG   MMIO_REG(0x14A, uint8_t)
#define RX_CTRL_REG_s   MMIO_REG(0x14A, struct __struct_RX_CTRL_REG)
#define RX_SYN_REG   MMIO_REG(0x155, uint8_t)
#define RX_SYN_REG_s   MMIO_REG(0x155, struct __struct_RX_SYN_REG)
#define SFD_VALUE_REG   MMIO_REG(0x14B, uint8_t)
#define SHORT_ADDR_0_REG   MMIO_REG(0x160, uint8_t)

Referenced by PHY_SetShortAddr().

#define SHORT_ADDR_1_REG   MMIO_REG(0x161, uint8_t)

Referenced by PHY_SetShortAddr().

#define TRX_CTRL_1_REG   MMIO_REG(0x144, uint8_t)
#define TRX_CTRL_1_REG_s   MMIO_REG(0x144, struct __struct_TRX_CTRL_1_REG)
#define TRX_CTRL_2_REG   MMIO_REG(0x14C, uint8_t)
#define TRX_CTRL_2_REG_s   MMIO_REG(0x14C, struct __struct_TRX_CTRL_2_REG)

Referenced by PHY_Init(), and PHY_TaskHandler().

#define TRX_FRAME_BUFFER (   index)    MMIO_REG(0x180 + (index), uint8_t)

Referenced by PHY_DataReq(), and PHY_TaskHandler().

#define TRX_STATE_REG   MMIO_REG(0x142, uint8_t)

Referenced by PHY_DataReq(), and phyTrxSetState().

#define TRX_STATE_REG_s   MMIO_REG(0x142, struct __struct_TRX_STATE_REG)

Referenced by PHY_TaskHandler().

#define TRX_STATUS_REG   MMIO_REG(0x141, uint8_t)
#define TRX_STATUS_REG_s   MMIO_REG(0x141, struct __struct_TRX_STATUS_REG)

Referenced by PHY_TaskHandler(), and phyTrxSetState().

#define TRXPR_REG   MMIO_REG(0x139, uint8_t)
#define TRXPR_REG_s   MMIO_REG(0x139, struct __struct_TRXPR_REG)

Referenced by PHY_Init(), PHY_Sleep(), and PHY_Wakeup().

#define TST_CTRL_DIGI_REG   MMIO_REG(0x176, uint8_t)
#define TST_RX_LENGTH_REG   MMIO_REG(0x17B, uint8_t)

Referenced by PHY_TaskHandler().

#define VERSION_NUM_REG   MMIO_REG(0x15D, uint8_t)
#define VREG_CTRL_REG   MMIO_REG(0x150, uint8_t)
#define VREG_CTRL_REG_s   MMIO_REG(0x150, struct __struct_VREG_CTRL_REG)
#define XAH_CTRL_0_REG   MMIO_REG(0x16C, uint8_t)
#define XAH_CTRL_0_REG_s   MMIO_REG(0x16C, struct __struct_XAH_CTRL_0_REG)
#define XAH_CTRL_1_REG   MMIO_REG(0x157, uint8_t)
#define XAH_CTRL_1_REG_s   MMIO_REG(0x157, struct __struct_XAH_CTRL_1_REG)
#define XOSC_CTRL_REG   MMIO_REG(0x152, uint8_t)
#define XOSC_CTRL_REG_s   MMIO_REG(0x152, struct __struct_XOSC_CTRL_REG)

typedef struct PHY_DataInd_t PHY_DataInd_t

anonymous enum
Enumerator
TRX_STATUS_P_ON 
TRX_STATUS_BUSY_RX 
TRX_STATUS_BUSY_TX 
TRX_STATUS_RX_ON 
TRX_STATUS_TRX_OFF 
TRX_STATUS_PLL_ON 
TRX_STATUS_SLEEP 
TRX_STATUS_BUSY_RX_AACK 
TRX_STATUS_BUSY_TX_ARET 
TRX_STATUS_RX_AACK_ON 
TRX_STATUS_TX_ARET_ON 
TRX_STATUS_RX_ON_NOCLK 
TRX_STATUS_RX_AACK_ON_NOCLK 
TRX_STATUS_BUSY_RX_AACK_NOCLK 
TRX_STATUS_STATE_TRANSITION_IN_PROGRESS 
anonymous enum
Enumerator
TRX_CMD_NOP 
TRX_CMD_TX_START 
TRX_CMD_FORCE_TRX_OFF 
TRX_CMD_FORCE_PLL_ON 
TRX_CMD_RX_ON 
TRX_CMD_TRX_OFF 
TRX_CMD_PLL_ON 
TRX_CMD_RX_AACK_ON 
TRX_CMD_TX_ARET_ON 
anonymous enum
Enumerator
TRAC_STATUS_SUCCESS 
TRAC_STATUS_SUCCESS_DATA_PENDING 
TRAC_STATUS_SUCCESS_WAIT_FOR_ACK 
TRAC_STATUS_CHANNEL_ACCESS_FAILURE 
TRAC_STATUS_NO_ACK 
TRAC_STATUS_INVALID 
anonymous enum
Enumerator
TX_PWR_3_5_DBM 
TX_PWR_3_3_DBM 
TX_PWR_2_8_DBM 
TX_PWR_2_3_DBM 
TX_PWR_1_8_DBM 
TX_PWR_1_2_DBM 
TX_PWR_0_5_DBM 
TX_PWR_MIN_0_5_DBM 
TX_PWR_MIN_1_5_DBM 
TX_PWR_MIN_2_5_DBM 
TX_PWR_MIN_3_5_DBM 
TX_PWR_MIN_4_5_DBM 
TX_PWR_MIN_6_5_DBM 
TX_PWR_MIN_8_5_DBM 
TX_PWR_MIN_11_5_DBM 
TX_PWR_MIN_16_5_DBM 
anonymous enum
Enumerator
TX_PWR_PA_LT_2US 
TX_PWR_PA_LT_4US 
TX_PWR_PA_LT_6US 
TX_PWR_PA_LT_8US 
anonymous enum
Enumerator
TX_PWR_PA_BUF_LT_0US 
TX_PWR_PA_BUF_LT_2US 
TX_PWR_PA_BUF_LT_4US 
TX_PWR_PA_BUF_LT_6US 
anonymous enum
Enumerator
PHY_STATUS_SUCCESS 
PHY_STATUS_CHANNEL_ACCESS_FAILURE 
PHY_STATUS_NO_ACK 
PHY_STATUS_ERROR 

void PHY_DataConf ( uint8_t  status)

References NwkIb_t::lock, NWK_TX_STATE_SENT, nwkIb, nwkTxConvertPhyStatus(), NwkFrame_t::state, and NwkFrame_t::tx.

Referenced by PHY_TaskHandler().

void PHY_DataInd ( PHY_DataInd_t *  ind)

References PHY_DataInd_t::data, NwkFrame_t::data, PHY_DataInd_t::lqi, NWK_RX_STATE_RECEIVED, nwkFrameAlloc(), PHY_DataInd_t::rssi, NwkFrame_t::rx, PHY_DataInd_t::size, NwkFrame_t::size, and NwkFrame_t::state.

Referenced by PHY_TaskHandler().

void PHY_DataReq ( uint8_t *  data)

References IRQ_CLEAR_VALUE, IRQ_STATUS_REG, PHY_CRC_SIZE, PHY_STATE_TX_WAIT_END, phyState, phyTrxSetState(), TRX_CMD_TX_ARET_ON, TRX_CMD_TX_START, TRX_FRAME_BUFFER, and TRX_STATE_REG.

Referenced by nwkTxTaskHandler().

int8_t PHY_EdReq ( void  )

References IRQ_STATUS_REG_s, PHY_ED_LEVEL_REG, PHY_RSSI_BASE_VAL, phySetRxState(), phyTrxSetState(), and TRX_CMD_RX_ON.

void PHY_EncryptReq ( uint8_t *  text,
uint8_t *  key 
)

References AES_DIR_ENCRYPT, AES_MODE_ECB, sal_aes_exec(), sal_aes_read(), and sal_aes_setup().

Referenced by SYS_EncryptReq().

void PHY_Init ( void  )

References CSMA_SEED_0_REG, PHY_RandomReq(), PHY_STATE_IDLE, phyRxState, phyState, phyTrxSetState(), sysclk_enable_peripheral_clock(), TRX_CMD_TRX_OFF, TRX_CTRL_2_REG_s, and TRXPR_REG_s.

Referenced by SYS_Init().

uint16_t PHY_RandomReq ( void  )

References delay_us, PHY_RSSI_REG_s, phySetRxState(), phyTrxSetState(), RANDOM_NUMBER_UPDATE_INTERVAL, and TRX_CMD_RX_ON.

Referenced by appInit(), and PHY_Init().

void PHY_SetChannel ( uint8_t  channel)

References PHY_CC_CCA_REG_s.

Referenced by appInit().

void PHY_SetIEEEAddr ( uint8_t *  ieee_addr)

References IEEE_ADDR_0_REG, IEEE_ADDR_1_REG, IEEE_ADDR_2_REG, IEEE_ADDR_3_REG, IEEE_ADDR_4_REG, IEEE_ADDR_5_REG, IEEE_ADDR_6_REG, and IEEE_ADDR_7_REG.

void PHY_SetPanId ( uint16_t  panId)

References PAN_ID_0_REG, and PAN_ID_1_REG.

Referenced by NWK_SetPanId().

void PHY_SetRxState ( bool  rx)

References phyRxState, and phySetRxState().

Referenced by appInit().

void PHY_SetShortAddr ( uint16_t  addr)

References CSMA_SEED_0_REG, SHORT_ADDR_0_REG, and SHORT_ADDR_1_REG.

Referenced by NWK_SetAddr().

void PHY_SetTxPower ( uint8_t  txPower)

References PHY_TX_PWR_REG_s.

void PHY_Sleep ( void  )

References PHY_STATE_SLEEP, phyState, phyTrxSetState(), TRX_CMD_TRX_OFF, and TRXPR_REG_s.

Referenced by NWK_SleepReq().

void PHY_TaskHandler ( void  )

References PHY_DataInd_t::data, IRQ_STATUS_REG_s, PHY_DataInd_t::lqi, PHY_CRC_SIZE, PHY_DataConf(), PHY_DataInd(), PHY_ED_LEVEL_REG, PHY_RSSI_BASE_VAL, PHY_STATE_IDLE, PHY_STATE_SLEEP, PHY_STATUS_CHANNEL_ACCESS_FAILURE, PHY_STATUS_ERROR, PHY_STATUS_NO_ACK, PHY_STATUS_SUCCESS, phyRxBuffer, phySetRxState(), phyState, PHY_DataInd_t::rssi, PHY_DataInd_t::size, TRAC_STATUS_CHANNEL_ACCESS_FAILURE, TRAC_STATUS_NO_ACK, TRAC_STATUS_SUCCESS, TRX_CTRL_2_REG_s, TRX_FRAME_BUFFER, TRX_STATE_REG_s, TRX_STATUS_REG_s, TRX_STATUS_RX_AACK_ON, TRX_STATUS_TX_ARET_ON, and TST_RX_LENGTH_REG.

Referenced by SYS_TaskHandler().

void PHY_Wakeup ( void  )

References PHY_STATE_IDLE, phySetRxState(), phyState, and TRXPR_REG_s.

Referenced by NWK_WakeupReq().

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