Chip-specific system clock manager configuration.

Macros
#define	CONFIG_DFLL0_DIV 4

#define	CONFIG_DFLL0_FREQ 48000000UL

#define	CONFIG_DFLL0_MUL ((4 * CONFIG_DFLL0_FREQ) / BOARD_OSC32_HZ)

#define	CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC32K

#define	CONFIG_PLL0_DIV 4 /* Fpll = (Fclk * PLL_mul) / PLL_div */

#define	CONFIG_PLL0_MUL

#define	CONFIG_PLL0_SOURCE PLL_SRC_OSC0

#define	CONFIG_SYSCLK_CPU_DIV 0

#define	CONFIG_SYSCLK_PBA_DIV 0

#define	CONFIG_SYSCLK_PBB_DIV 0

#define	CONFIG_SYSCLK_PBC_DIV 0

#define	CONFIG_SYSCLK_PBD_DIV 0

#define	CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0

#define	CONFIG_USBCLK_DIV 1

#define	CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0

#define CONFIG_DFLL0_DIV 4

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_FREQ 48000000UL

#define CONFIG_DFLL0_MUL ((4 * CONFIG_DFLL0_FREQ) / BOARD_OSC32_HZ)

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_SOURCE GENCLK_SRC_OSC32K

Referenced by dfll_enable_config_defaults().

#define CONFIG_PLL0_DIV 4 /* Fpll = (Fclk * PLL_mul) / PLL_div */

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_MUL

Value:

(192000000 / FOSC0) /* Fpll = (Fclk *
                                                       * PLL_mul) / PLL_div
                                                       **/

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0

Referenced by pll_enable_config_defaults().

#define CONFIG_SYSCLK_CPU_DIV 0

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBA_DIV 0

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBB_DIV 0

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBC_DIV 0

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBD_DIV 0