The AT86RF233 is a feature rich, low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate sub 1GHz ISM band applications Refer AT86RF233 Data Sheet for detailed information .
#define AACK_ACK_TIME 2 |
#define AACK_DIS_ACK 4 |
#define AACK_FLTR_RES_FT 5 |
#define AACK_FVN_MODE 6 |
#define AACK_I_AM_COORD 3 |
#define AACK_PROM_MODE 1 |
#define AACK_SET_PD 5 |
#define AACK_SPC_EN 0 |
#define AACK_UPLD_RES_FT 4 |
#define AES_BLOCK_SIZE 16 |
#define AES_CORE_CYCLE_TIME 24 /* us */ |
#define AES_CTRL_DIR 3 |
#define AES_CTRL_M_REG 0x94 |
#define AES_CTRL_MODE 4 |
#define AES_CTRL_REG 0x83 |
#define AES_CTRL_REQUEST 7 |
#define AES_KEY_REG 0x84 |
#define AES_STATE_REG 0x84 |
#define AES_STATUS_DONE 0 |
#define AES_STATUS_ER 7 |
#define AES_STATUS_REG 0x82 |
#define AGC_HOLD 2 |
#define AGC_HOLD_SEL 5 |
#define AGC_OFF 3 |
#define AGC_RST 4 |
#define AMI 5 |
#define ANT_CTRL 0 |
#define ANT_DIV_EN 3 |
#define ANT_DIV_REG 0x0d |
#define ANT_EXT_SW_EN 2 |
#define ANT_SEL 7 |
#define ARET_CSMA_RETRIES 1 |
#define ARET_FRAME_RETRIES 4 |
#define ARET_TX_TS_EN 7 |
#define AVDD_OK 6 |
#define AVREG_EXT 7 |
#define BAT_LOW 7 |
#define BATMON_HR 4 |
#define BATMON_OK 5 |
#define BATMON_REG 0x11 |
#define BATMON_VTH 0 |
#define CCA_DONE 7 |
#define CCA_ED_DONE 4 |
Referenced by PHY_EdReq().
#define CCA_ED_THRES 0 |
#define CCA_MODE 5 |
#define CCA_REQUEST 7 |
#define CCA_STATUS 6 |
#define CCA_THRES_REG 0x09 |
#define CHANNEL 0 |
#define CLKM_CTRL 0 |
#define CLKM_SHA_SEL 3 |
#define CSMA_BE_REG 0x2f |
#define CSMA_SEED_0_REG 0x2d |
Referenced by PHY_SetShortAddr().
#define CSMA_SEED_1 0 |
#define CSMA_SEED_1_REG 0x2e |
#define DVDD_OK 2 |
#define DVREG_EXT 3 |
#define FTN_CTRL_REG 0x18 |
#define FTN_START 7 |
#define FTNV 0 |
#define GC 0 |
#define IEEE_ADDR_0_REG 0x24 |
Referenced by PHY_SetIEEEAddr().
#define IEEE_ADDR_1_REG 0x25 |
#define IEEE_ADDR_2_REG 0x26 |
#define IEEE_ADDR_3_REG 0x27 |
#define IEEE_ADDR_4_REG 0x28 |
#define IEEE_ADDR_5_REG 0x29 |
#define IEEE_ADDR_6_REG 0x2a |
#define IEEE_ADDR_7_REG 0x2b |
#define IPAN_RPC_EN 1 |
#define IRC_TX_TIME 0 |
#define IRQ_2_EXT_EN 6 |
#define IRQ_MASK_MODE 1 |
Referenced by PHY_Init().
#define IRQ_MASK_REG 0x0e |
#define IRQ_POLARITY 0 |
#define IRQ_STATUS_REG 0x0f |
Referenced by PHY_DataReq(), PHY_EdReq(), PHY_TaskHandler(), and phySetRxState().
#define MAN_ID_0_REG 0x1e |
#define MAN_ID_1_REG 0x1f |
#define MAX_BE 4 |
#define MAX_CSMA_RETRES 1 |
#define MAX_FRAME_RETRES 4 |
#define MIN_BE 0 |
#define MOD 6 |
#define MOD_SEL 7 |
#define OQPSK_DATA_RATE 0 |
#define OQPSK_SCRAM_EN 5 |
Referenced by PHY_Init().
#define PA_EXT_EN 7 |
#define PAN_ID_0_REG 0x22 |
Referenced by PHY_SetPanId().
#define PAN_ID_1_REG 0x23 |
Referenced by PHY_SetPanId().
#define PART_NUM_REG 0x1c |
#define PDT_RPC_EN 4 |
#define PDT_THRES 0 |
#define PEL_SHIFT_VALUE 6 |
#define PHY_CC_CCA_REG 0x08 |
Referenced by PHY_SetChannel().
#define PHY_ED_LEVEL_REG 0x07 |
Referenced by PHY_EdReq(), and PHY_TaskHandler().
#define PHY_HAS_AES_MODULE |
#define PHY_HAS_RANDOM_NUMBER_GENERATOR |
#define PHY_PMU_VALUE_REG 0x3b |
#define PHY_RSSI_BASE_VAL (-91) |
Referenced by PHY_EdReq(), and PHY_TaskHandler().
#define PHY_RSSI_REG 0x06 |
Referenced by PHY_RandomReq().
#define PHY_TX_PWR_REG 0x05 |
Referenced by PHY_SetTxPower().
#define PHY_TX_TIME_REG 0x3b |
#define PLL_CF 0 |
#define PLL_CF_REG 0x1a |
#define PLL_CF_START 7 |
#define PLL_DCU_REG 0x1b |
#define PLL_DCU_START 7 |
#define PLL_LOCK 0 |
#define PLL_RPC_EN 3 |
#define PLL_UNLOCK 1 |
#define PMU_EN 4 |
#define PMU_IF_INVERSE 4 |
#define RANDOM_NUMBER_UPDATE_INTERVAL 1 /* us */ |
Referenced by PHY_RandomReq().
#define RF_CMD_FRAME_R ((0 << 7) | (0 << 6) | (1 << 5)) |
#define RF_CMD_FRAME_W ((0 << 7) | (1 << 6) | (1 << 5)) |
#define RF_CMD_REG_R ((1 << 7) | (0 << 6)) |
#define RF_CMD_REG_W ((1 << 7) | (1 << 6)) |
#define RF_CMD_SRAM_R ((0 << 7) | (0 << 6) | (0 << 5)) |
#define RF_CMD_SRAM_W ((0 << 7) | (1 << 6) | (0 << 5)) |
#define RND_VALUE 5 |
Referenced by PHY_RandomReq().
#define RSSI 0 |
#define RX_BL_CTRL 4 |
#define RX_CRC_VALID 7 |
#define RX_CTRL_REG 0x0a |
#define RX_PDT_DIS 7 |
#define RX_PDT_LEVEL 0 |
#define RX_RPC_CTRL 6 |
#define RX_RPC_EN 5 |
#define RX_SAFE_MODE 7 |
Referenced by PHY_Init().
#define RX_START 2 |
#define RX_SYN_REG 0x15 |
#define SFD_VALUE_REG 0x0b |
#define SHORT_ADDR_0_REG 0x20 |
Referenced by PHY_SetShortAddr().
#define SHORT_ADDR_1_REG 0x21 |
Referenced by PHY_SetShortAddr().
#define SLOTTED_OPERATION 0 |
#define SPI_CMD_MODE 2 |
Referenced by PHY_Init().
#define TOM_EN 7 |
#define TRAC_STATUS 5 |
Referenced by PHY_TaskHandler().
#define TRAC_STATUS_CHANNEL_ACCESS_FAILURE 3 |
Referenced by PHY_TaskHandler().
#define TRAC_STATUS_INVALID 7 |
#define TRAC_STATUS_NO_ACK 5 |
Referenced by PHY_TaskHandler().
#define TRAC_STATUS_SUCCESS 0 |
Referenced by PHY_TaskHandler().
#define TRAC_STATUS_SUCCESS_DATA_PENDING 1 |
#define TRAC_STATUS_SUCCESS_WAIT_FOR_ACK 2 |
#define TRX_CMD 0 |
#define TRX_CMD_FORCE_PLL_ON 4 |
#define TRX_CMD_FORCE_TRX_OFF 3 |
Referenced by phyTrxSetState().
#define TRX_CMD_NOP 0 |
#define TRX_CMD_PLL_ON 9 |
#define TRX_CMD_RX_AACK_ON 22 |
Referenced by phySetRxState().
#define TRX_CMD_RX_ON 6 |
Referenced by PHY_EdReq(), and PHY_RandomReq().
#define TRX_CMD_TRX_OFF 8 |
Referenced by PHY_Init(), PHY_Sleep(), and phySetRxState().
#define TRX_CMD_TX_ARET_ON 25 |
Referenced by PHY_DataReq().
#define TRX_CMD_TX_START 2 |
#define TRX_CTRL_0_REG 0x03 |
#define TRX_CTRL_1_REG 0x04 |
Referenced by PHY_Init().
#define TRX_CTRL_2_REG 0x0c |
Referenced by PHY_Init().
#define TRX_END 3 |
Referenced by PHY_TaskHandler().
#define TRX_RPC_REG 0x16 |
#define TRX_STATE_REG 0x02 |
Referenced by PHY_Init(), PHY_TaskHandler(), and phyTrxSetState().
#define TRX_STATUS 0 |
#define TRX_STATUS_BUSY_RX 1 |
#define TRX_STATUS_BUSY_RX_AACK 17 |
#define TRX_STATUS_BUSY_RX_AACK_NOCLK 30 |
#define TRX_STATUS_BUSY_TX 2 |
#define TRX_STATUS_BUSY_TX_ARET 18 |
#define TRX_STATUS_MASK 0x1f |
Referenced by PHY_Init(), phyTrxSetState(), and phyWaitState().
#define TRX_STATUS_P_ON 0 |
#define TRX_STATUS_PLL_ON 9 |
#define TRX_STATUS_REG 0x01 |
Referenced by PHY_Init(), phyTrxSetState(), and phyWaitState().
#define TRX_STATUS_RX_AACK_ON 22 |
Referenced by PHY_TaskHandler().
#define TRX_STATUS_RX_AACK_ON_NOCLK 29 |
#define TRX_STATUS_RX_ON 6 |
#define TRX_STATUS_RX_ON_NOCLK 28 |
#define TRX_STATUS_SLEEP 15 |
#define TRX_STATUS_STATE_TRANSITION 31 |
#define TRX_STATUS_TRX_OFF 8 |
Referenced by PHY_Init(), and phyTrxSetState().
#define TRX_STATUS_TX_ARET_ON 25 |
#define TRX_UR 6 |
#define TST_AGC_REG 0x3c |
#define TST_CTRL_DIG 0 |
#define TST_CTRL_DIGI_REG 0x36 |
#define TST_SDM_REG 0x3d |
#define TX_AUTO_CRC_ON 5 |
Referenced by PHY_Init().
#define TX_PWR 0 |
#define TX_RX 5 |
#define TX_RX_SEL 4 |
#define VERSION_NUM_REG 0x1d |
#define VREG_CTRL_REG 0x10 |
#define XAH_CTRL_0_REG 0x2c |
#define XAH_CTRL_1_REG 0x17 |
#define XAH_CTRL_2_REG 0x19 |
#define XAH_TX_RPC_EN 2 |
#define XOSC_CTRL_REG 0x12 |
#define XTAL_MODE 4 |
#define XTAL_TRIM 0 |
typedef struct PHY_DataInd_t PHY_DataInd_t |
anonymous enum |
void PHY_DataConf | ( | uint8_t | status | ) |
References NwkIb_t::lock, NWK_TX_STATE_SENT, nwkIb, nwkTxConvertPhyStatus(), NwkFrame_t::state, and NwkFrame_t::tx.
Referenced by PHY_TaskHandler().
void PHY_DataInd | ( | PHY_DataInd_t * | ind | ) |
References PHY_DataInd_t::data, NwkFrame_t::data, PHY_DataInd_t::lqi, NWK_RX_STATE_RECEIVED, nwkFrameAlloc(), PHY_DataInd_t::rssi, NwkFrame_t::rx, PHY_DataInd_t::size, NwkFrame_t::size, and NwkFrame_t::state.
Referenced by PHY_TaskHandler().
void PHY_DataReq | ( | uint8_t * | data | ) |
References IRQ_STATUS_REG, PHY_STATE_TX_WAIT_END, phyReadRegister(), phyState, phyTrxSetState(), TRX_CMD_TX_ARET_ON, trx_frame_write(), TRX_SLP_TR_HIGH, TRX_SLP_TR_LOW, and TRX_TRIG_DELAY.
Referenced by nwkTxTaskHandler().
int8_t PHY_EdReq | ( | void | ) |
void PHY_EncryptReq | ( | uint8_t * | text, |
uint8_t * | key | ||
) |
References AES_DIR_ENCRYPT, AES_MODE_ECB, sal_aes_exec(), sal_aes_read(), sal_aes_setup(), and sal_aes_wrrd().
Referenced by SYS_EncryptReq().
void PHY_Init | ( | void | ) |
References IRQ_MASK_MODE, OQPSK_SCRAM_EN, PHY_STATE_IDLE, phyReadRegister(), PhyReset(), phyRxState, phyState, phyWriteRegister(), RX_SAFE_MODE, SPI_CMD_MODE, TRX_CMD_TRX_OFF, TRX_CTRL_1_REG, TRX_CTRL_2_REG, trx_spi_init(), TRX_STATE_REG, TRX_STATUS_MASK, TRX_STATUS_REG, TRX_STATUS_TRX_OFF, and TX_AUTO_CRC_ON.
Referenced by SYS_Init().
uint16_t PHY_RandomReq | ( | void | ) |
References delay_us, PHY_RSSI_REG, phyReadRegister(), phySetRxState(), phyTrxSetState(), RANDOM_NUMBER_UPDATE_INTERVAL, RND_VALUE, and TRX_CMD_RX_ON.
Referenced by appInit().
void PHY_SetChannel | ( | uint8_t | channel | ) |
References PHY_CC_CCA_REG, phyReadRegister(), and phyWriteRegister().
Referenced by appInit().
void PHY_SetIEEEAddr | ( | uint8_t * | ieee_addr | ) |
References IEEE_ADDR_0_REG, and trx_reg_write().
void PHY_SetPanId | ( | uint16_t | panId | ) |
References PAN_ID_0_REG, PAN_ID_1_REG, and phyWriteRegister().
Referenced by NWK_SetPanId().
void PHY_SetRxState | ( | bool | rx | ) |
References phyRxState, and phySetRxState().
Referenced by appInit().
void PHY_SetShortAddr | ( | uint16_t | addr | ) |
References CSMA_SEED_0_REG, phyWriteRegister(), SHORT_ADDR_0_REG, and SHORT_ADDR_1_REG.
Referenced by NWK_SetAddr().
void PHY_SetTxPower | ( | uint8_t | txPower | ) |
References PHY_TX_PWR_REG, phyReadRegister(), and phyWriteRegister().
void PHY_Sleep | ( | void | ) |
References PHY_STATE_SLEEP, phyState, phyTrxSetState(), TRX_CMD_TRX_OFF, and TRX_SLP_TR_HIGH.
Referenced by NWK_SleepReq().
void PHY_TaskHandler | ( | void | ) |
References PHY_DataInd_t::data, IRQ_STATUS_REG, PHY_DataInd_t::lqi, PHY_CRC_SIZE, PHY_DataConf(), PHY_DataInd(), PHY_ED_LEVEL_REG, PHY_RSSI_BASE_VAL, PHY_STATE_IDLE, PHY_STATE_SLEEP, PHY_STATE_TX_WAIT_END, PHY_STATUS_CHANNEL_ACCESS_FAILURE, PHY_STATUS_ERROR, PHY_STATUS_NO_ACK, PHY_STATUS_SUCCESS, phyReadRegister(), phyRxBuffer, phySetRxState(), phyState, phyWaitState(), PHY_DataInd_t::rssi, PHY_DataInd_t::size, TRAC_STATUS, TRAC_STATUS_CHANNEL_ACCESS_FAILURE, TRAC_STATUS_NO_ACK, TRAC_STATUS_SUCCESS, TRX_END, trx_frame_read(), TRX_STATE_REG, and TRX_STATUS_RX_AACK_ON.
Referenced by SYS_TaskHandler().
void PHY_Wakeup | ( | void | ) |
References PHY_STATE_IDLE, phySetRxState(), phyState, and TRX_SLP_TR_LOW.
Referenced by NWK_WakeupReq().