avr32/applications/uc3-bluetooth-t2bf-spp-demo/conf/conf_clock.h File Reference

Atmel Development Board Clock Configuration (ASF)

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

Macros
#define	CONFIG_PLL0_DIV   (1)
#define	CONFIG_PLL0_MUL   (48000000UL / BOARD_OSC0_HZ)
#define	CONFIG_PLL0_SOURCE   (PLL_SRC_OSC0)
#define	CONFIG_PLL1_DIV   (2)
#define	CONFIG_PLL1_MUL   (8)
#define	CONFIG_PLL1_SOURCE   (PLL_SRC_OSC0)
#define	CONFIG_SYSCLK_CPU_DIV   (0)
#define	CONFIG_SYSCLK_PBA_DIV   (1)
#define	CONFIG_SYSCLK_PBB_DIV   (0)
#define	CONFIG_SYSCLK_SOURCE   (SYSCLK_SRC_PLL0)
#define	CONFIG_USBCLK_DIV   (1)
#define	CONFIG_USBCLK_SOURCE   (USBCLK_SRC_PLL0)

#define CONFIG_PLL0_DIV   (1)

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_MUL   (48000000UL / BOARD_OSC0_HZ)

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_SOURCE   (PLL_SRC_OSC0)

Referenced by pll_enable_config_defaults(), and run_pll_dfll_test().

#define CONFIG_PLL1_DIV   (2)

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL1_MUL   (8)

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL1_SOURCE   (PLL_SRC_OSC0)

Referenced by pll_enable_config_defaults(), and run_pll_dfll_test().

#define CONFIG_SYSCLK_CPU_DIV   (0)

#define CONFIG_SYSCLK_PBA_DIV   (1)

#define CONFIG_SYSCLK_PBB_DIV   (0)

#define CONFIG_SYSCLK_SOURCE   (SYSCLK_SRC_PLL0)

#define CONFIG_USBCLK_DIV   (1)

#define CONFIG_USBCLK_SOURCE   (USBCLK_SRC_PLL0)