MEMORY - SDRAM MT48LC16M16A2TG7E

This a configuration for the MT48LC16M16A2TG7E SDRAM from Mircon.

This configuration will be used by the EBI driver to set up e.g. bus width and timing for the SDRAM controller.

Modules
	Related Project(s)
	In this section you can find all the projects related to the MEMORY - SDRAM MT48LC16M16A2TG7E.

Macros
#define	SDRAM_BANK_BITS   2
	The number of bank bits for this SDRAM (1 or 2). More...
#define	SDRAM_CAS   2
	The minimal column address select (READ) latency for this SDRAM (1 to 3 SDRAM cycles). More...
#define	SDRAM_COL_BITS   9
	The number of column bits for this SDRAM (8 to 11). More...
#define	SDRAM_INIT_AUTO_REFRESH_COUNT   2
	The minimal number of AUTO REFRESH commands required during initialization for this SDRAM. More...
#define	SDRAM_ROW_BITS   13
	The number of row bits for this SDRAM (11 to 13). More...
#define	SDRAM_STABLE_CLOCK_INIT_DELAY   100
	The minimal stable-clock initialization delay for this SDRAM. More...
#define	SDRAM_TMRD   2
	The minimal mode register delay time for this SDRAM. More...
#define	SDRAM_TR   7812
	The maximal refresh time for this SDRAM (0 to 4095 SDRAM cycles). More...
#define	SDRAM_TRAS   37
	The minimal row address select time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TRC   60
	The minimal row cycle time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TRCD   15
	The minimal row to column delay time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TRFC   66
	The minimal refresh cycle time for this SDRAM. More...
#define	SDRAM_TRP   15
	The minimal row precharge time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TWR   14
	The minimal write recovery time for this SDRAM (0 to 15 SDRAM cycles). More...
#define	SDRAM_TXSR   67
	The minimal exit self refresh time for this SDRAM (0 to 15 SDRAM cycles). More...

#define SDRAM_BANK_BITS   2

The number of bank bits for this SDRAM (1 or 2).

Referenced by sdramc_init().

#define SDRAM_CAS   2

The minimal column address select (READ) latency for this SDRAM (1 to 3 SDRAM cycles).

Unit: tCK (SDRAM cycle period).

Referenced by sdramc_init().

#define SDRAM_COL_BITS   9

The number of column bits for this SDRAM (8 to 11).

Referenced by sdramc_init().

#define SDRAM_INIT_AUTO_REFRESH_COUNT   2

The minimal number of AUTO REFRESH commands required during initialization for this SDRAM.

Referenced by sdramc_init().

#define SDRAM_ROW_BITS   13

The number of row bits for this SDRAM (11 to 13).

Referenced by sdramc_init().

#define SDRAM_STABLE_CLOCK_INIT_DELAY   100

The minimal stable-clock initialization delay for this SDRAM.

Unit: us.

Referenced by sdramc_init().

#define SDRAM_TMRD   2

The minimal mode register delay time for this SDRAM.

LOAD MODE REGISTER command to ACTIVE or REFRESH command delay. Unit: tCK (SDRAM cycle period).

Referenced by sdramc_init().

#define SDRAM_TR   7812

The maximal refresh time for this SDRAM (0 to 4095 SDRAM cycles).

Refresh period. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRAS   37

The minimal row address select time for this SDRAM (0 to 15 SDRAM cycles).

ACTIVE-to-PRECHARGE command delay. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRC   60

The minimal row cycle time for this SDRAM (0 to 15 SDRAM cycles).

ACTIVE-to-ACTIVE command delay. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRCD   15

The minimal row to column delay time for this SDRAM (0 to 15 SDRAM cycles).

ACTIVE-to-READ/WRITE command delay. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRFC   66

The minimal refresh cycle time for this SDRAM.

AUTO REFRESH command period. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRP   15

The minimal row precharge time for this SDRAM (0 to 15 SDRAM cycles).

PRECHARGE command period. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TWR   14

The minimal write recovery time for this SDRAM (0 to 15 SDRAM cycles).

Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TXSR   67

The minimal exit self refresh time for this SDRAM (0 to 15 SDRAM cycles).

Exit SELF REFRESH to ACTIVE command delay. Unit: ns.

Referenced by sdramc_init().