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Chip-specific system clock manager configuration.

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

Macros
#define	CONFIG_CPU_HZ 12000000

#define	CONFIG_DFLL0_DIV 1 /* Fdfll = (Fclk * mul) / div */

#define	CONFIG_DFLL0_FREQ 96025000

#define	CONFIG_DFLL0_MUL 835 /* Fdfll = (Fclk * mul) / div */

#define	CONFIG_DFLL0_SOURCE GENCLK_SRC_RCSYS

#define	CONFIG_GENERIC_CLOCK 28750

#define	CONFIG_GENERIC_DIV 1

#define	CONFIG_GENERIC_ID 2

#define	CONFIG_GENERIC_SRC GENCLK_SRC_RCSYS

#define	CONFIG_PBA_HZ 6000000

#define	CONFIG_PBB_HZ 6000000

#define	CONFIG_PBC_HZ 6000000

#define	CONFIG_PBD_HZ 6000000

#define	CONFIG_PLL0_DIV 1

#define	CONFIG_PLL0_MUL (48000000UL / BOARD_OSC0_HZ)

#define	CONFIG_PLL0_SOURCE PLL_SRC_OSC0

#define	CONFIG_RCFAST_FRANGE 2

#define	CONFIG_SYSCLK_CPU_DIV 0

#define	CONFIG_SYSCLK_PBA_DIV 1

#define	CONFIG_SYSCLK_PBB_DIV 1

#define	CONFIG_SYSCLK_PBC_DIV 1

#define	CONFIG_SYSCLK_PBD_DIV 1

#define	CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCFAST

#define	get_generic_clock()

#define	PLL0 0

#define CONFIG_CPU_HZ 12000000

Referenced by run_sync_clock_test().

#define CONFIG_DFLL0_DIV 1 /* Fdfll = (Fclk * mul) / div */

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_FREQ 96025000

#define CONFIG_DFLL0_MUL 835 /* Fdfll = (Fclk * mul) / div */

Referenced by dfll_enable_config_defaults().

#define CONFIG_DFLL0_SOURCE GENCLK_SRC_RCSYS

Referenced by dfll_enable_config_defaults().

#define CONFIG_GENERIC_CLOCK 28750

Referenced by run_generic_clock_test().

#define CONFIG_GENERIC_DIV 1

Referenced by run_generic_clock_test().

#define CONFIG_GENERIC_ID 2

Referenced by cleanup_generic_clock_test(), and run_generic_clock_test().

#define CONFIG_GENERIC_SRC GENCLK_SRC_RCSYS

Referenced by run_generic_clock_test().

#define CONFIG_PBA_HZ 6000000

Referenced by run_sync_clock_test().

#define CONFIG_PBB_HZ 6000000

Referenced by run_sync_clock_test().

#define CONFIG_PBC_HZ 6000000

Referenced by run_sync_clock_test().

#define CONFIG_PBD_HZ 6000000

Referenced by run_sync_clock_test().

#define CONFIG_PLL0_DIV 1

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_MUL (48000000UL / BOARD_OSC0_HZ)

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0

Referenced by pll_enable_config_defaults(), and run_pll_dfll_test().

#define CONFIG_RCFAST_FRANGE 2

Referenced by osc_priv_enable_rcfast(), and sysclk_get_main_hz().

#define CONFIG_SYSCLK_CPU_DIV 0

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBA_DIV 1

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBB_DIV 1

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBC_DIV 1

Referenced by sysclk_init().

#define CONFIG_SYSCLK_PBD_DIV 1

Referenced by sysclk_init().

#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCFAST

Referenced by sysclk_init().

#define get_generic_clock ( )

Value:

(CONFIG_GENERIC_DIV == 0 ? osc_get_rate(OSC_ID_RCSYS) \

: osc_get_rate(OSC_ID_RCSYS) / (2*(CONFIG_GENERIC_DIV + 1)))

static uint32_t osc_get_rate(uint8_t id)

Return the frequency of oscillator id in Hz.

Definition: sam4l/osc.h:447

CONFIG_GENERIC_DIV

#define CONFIG_GENERIC_DIV

Definition: conf_clock.h:77

#define OSC_ID_RCSYS

Internal System RC oscillator.

Definition: sam4l/osc.h:59

Referenced by run_generic_clock_test().

#define PLL0 0

Referenced by cleanup_pll_dfll_test(), and run_pll_dfll_test().