This group contains functions and definitions related to configuring and enabling/disabling on-chip PLLs.
A PLL will take an input signal (the source), optionally divide the frequency by a configurable divider, and then multiply the frequency by a configurable multiplier.
Some devices don't support input dividers; specifying any other divisor than 1 on these devices will result in an assertion failure. Other devices may have various restrictions to the frequency range of the input and output signals.
The following example shows how to configure and enable PLL0 using the default parameters specified using the configuration symbols listed above.
To configure, enable PLL0 using the default parameters and to disable a specific feature like Wide Bandwidth Mode (a UC3A3-specific PLL option.), you can use this initialization process.
When the last function call returns, PLL0 is ready to be used as the main system clock source.
Each PLL has a set of default parameters determined by the following configuration symbols in the application's configuration file:
These configuration symbols determine the result of calling pll_config_defaults() and pll_get_default_rate().
Data Structures | |
struct | pll_config |
Hardware-specific representation of PLL configuration. More... | |
Macros | |
#define | PLL_TIMEOUT_MS div_ceil(1000 * (PLL_MAX_STARTUP_CYCLES * 2), OSC_RCSYS_MIN_HZ) |
Number of milliseconds to wait for PLL lock. More... | |
Enumerations | |
enum | pll_source { PLL_SRC_OSC0 = 0, PLL_SRC_GCLK9 = 1, PLL_NR_SOURCES } |
PLL clock source. More... | |
Functions | |
static void | pll_config_clear_option (struct pll_config *cfg, uint32_t option) |
static void | pll_config_init (struct pll_config *cfg, enum pll_source src, uint32_t divide, uint32_t mul) |
The PLL options PLL_OPT_VCO_RANGE_HIGH and PLL_OPT_OUTPUT_DIV will be set automatically based on the calculated target frequency. More... | |
static void | pll_config_read (struct pll_config *cfg, uint32_t pll_id) |
static void | pll_config_set_option (struct pll_config *cfg, uint32_t option) |
void | pll_config_write (const struct pll_config *cfg, uint32_t pll_id) |
void | pll_disable (uint32_t pll_id) |
void | pll_enable (const struct pll_config *cfg, uint32_t pll_id) |
static void | pll_enable_config_defaults (uint32_t pll_id) |
static bool | pll_is_locked (uint32_t pll_id) |
Chip-specific PLL characteristics | |
#define | PLL_MAX_STARTUP_CYCLES (SCIF_PLL_PLLCOUNT_Msk >> SCIF_PLL_PLLCOUNT_Pos) |
Maximum PLL startup time in number of slow clock cycles. More... | |
#define | NR_PLLS 1 |
Number of on-chip PLLs. More... | |
#define | PLL_MIN_HZ 40000000 |
Minimum frequency that the PLL can generate. More... | |
#define | PLL_MAX_HZ 240000000 |
Maximum frequency that the PLL can generate. More... | |
PLL configuration | |
#define | pll_config_defaults(cfg, pll_id) |
Initialize PLL configuration using default parameters. More... | |
#define | pll_get_default_rate(pll_id) |
Get the default rate in Hz of pll_id. More... | |
Interaction with the PLL hardware | |
static int | pll_wait_for_lock (unsigned int pll_id) |
Wait for PLL pll_id to become locked. More... | |
static void | pll_enable_source (enum pll_source src) |
Enable the source of the pll. More... | |
Chip-specific PLL options | |
#define | PLL_NR_OPTIONS 3 |
Number of PLL option bits. More... | |
#define | PLL_OPT_VCO_RANGE_HIGH 0 |
VCO frequency range is 160-240 MHz (80-180 MHz if unset). More... | |
#define | PLL_OPT_OUTPUT_DIV 1 |
Divide output frequency by two. More... | |
#define | PLL_OPT_WBM_DISABLE 2 |
Disable wide-bandwidth mode. More... | |
#define | PLL_VCO_LOW_THRESHOLD |
The threshold above which to set the PLL_OPT_VCO_RANGE_HIGH option. More... | |
#define NR_PLLS 1 |
Number of on-chip PLLs.
Referenced by pll_config_read(), pll_config_write(), pll_disable(), pll_enable(), pll_is_locked(), and pll_wait_for_lock().
#define pll_config_defaults | ( | cfg, | |
pll_id | |||
) |
Initialize PLL configuration using default parameters.
After this function returns, cfg will contain a configuration which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) times the frequency of CONFIG_PLLx_SOURCE.
cfg | The PLL configuration to be initialized. |
pll_id | Use defaults for this PLL. |
Referenced by run_pll_dfll_test().
#define pll_get_default_rate | ( | pll_id | ) |
Get the default rate in Hz of pll_id.
Referenced by sysclk_get_main_hz().
#define PLL_MAX_HZ 240000000 |
Maximum frequency that the PLL can generate.
Referenced by pll_config_init().
#define PLL_MAX_STARTUP_CYCLES (SCIF_PLL_PLLCOUNT_Msk >> SCIF_PLL_PLLCOUNT_Pos) |
Maximum PLL startup time in number of slow clock cycles.
Referenced by pll_config_init(), and run_pll_dfll_test().
#define PLL_MIN_HZ 40000000 |
Minimum frequency that the PLL can generate.
Referenced by pll_config_init().
#define PLL_NR_OPTIONS 3 |
Number of PLL option bits.
Number of PLL options.
Referenced by pll_config_clear_option(), and pll_config_set_option().
#define PLL_OPT_OUTPUT_DIV 1 |
Divide output frequency by two.
Referenced by pll_config_init().
#define PLL_OPT_VCO_RANGE_HIGH 0 |
VCO frequency range is 160-240 MHz (80-180 MHz if unset).
Referenced by pll_config_init().
#define PLL_OPT_WBM_DISABLE 2 |
Disable wide-bandwidth mode.
#define PLL_TIMEOUT_MS div_ceil(1000 * (PLL_MAX_STARTUP_CYCLES * 2), OSC_RCSYS_MIN_HZ) |
Number of milliseconds to wait for PLL lock.
#define PLL_VCO_LOW_THRESHOLD |
The threshold above which to set the PLL_OPT_VCO_RANGE_HIGH option.
Referenced by pll_config_init().
enum pll_source |
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inlinestatic |
References Assert, pll_config::ctrl, and PLL_NR_OPTIONS.
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inlinestatic |
The PLL options PLL_OPT_VCO_RANGE_HIGH and PLL_OPT_OUTPUT_DIV will be set automatically based on the calculated target frequency.
References Assert, pll_config::ctrl, DIV_MAX, DIV_MIN, MUL_MAX, MUL_MIN, osc_get_rate(), pll_config_set_option(), PLL_MAX_HZ, PLL_MAX_STARTUP_CYCLES, PLL_MIN_HZ, PLL_NR_SOURCES, PLL_OPT_OUTPUT_DIV, PLL_OPT_VCO_RANGE_HIGH, and PLL_VCO_LOW_THRESHOLD.
Referenced by pll_enable_config_defaults().
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inlinestatic |
References Assert, pll_config::ctrl, and NR_PLLS.
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inlinestatic |
References Assert, pll_config::ctrl, and PLL_NR_OPTIONS.
Referenced by pll_config_init().
void pll_config_write | ( | const struct pll_config * | cfg, |
uint32_t | pll_id | ||
) |
References Assert, cpu_irq_restore(), cpu_irq_save(), pll_config::ctrl, NR_PLLS, and SCIF_UNLOCK_PLL_REG.
void pll_disable | ( | uint32_t | pll_id | ) |
References Assert, cpu_irq_restore(), cpu_irq_save(), NR_PLLS, and SCIF_UNLOCK_PLL_REG.
Referenced by cleanup_pll_dfll_test().
void pll_enable | ( | const struct pll_config * | cfg, |
uint32_t | pll_id | ||
) |
References Assert, cpu_irq_restore(), cpu_irq_save(), pll_config::ctrl, NR_PLLS, and SCIF_UNLOCK_PLL_REG.
Referenced by pll_enable_config_defaults(), and run_pll_dfll_test().
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inlinestatic |
References Assert, CONFIG_PLL0_DIV, CONFIG_PLL0_MUL, CONFIG_PLL0_SOURCE, pll_config_init(), pll_enable(), pll_enable_source(), and pll_is_locked().
Referenced by genclk_enable_source(), and sysclk_init().
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inlinestatic |
Enable the source of the pll.
The source is enabled, if the source is not already running.
src | The ID of the PLL source to enable. |
References Assert, osc_enable(), OSC_ID_OSC0, osc_is_ready(), osc_wait_ready(), PLL_SRC_GCLK9, and PLL_SRC_OSC0.
Referenced by pll_enable_config_defaults(), and run_pll_dfll_test().
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inlinestatic |
References Assert, and NR_PLLS.
Referenced by pll_enable_config_defaults(), pll_wait_for_lock(), and run_pll_dfll_test().
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inlinestatic |
Wait for PLL pll_id to become locked.
pll_id | The ID of the PLL to wait for. |
STATUS_OK | The PLL is now locked. |
ERR_TIMEOUT | Timed out waiting for PLL to become locked. |
References Assert, NR_PLLS, and pll_is_locked().