Clock system configuration for clock example 2.
Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_PLL0_DIV 1 |
#define | CONFIG_PLL0_MUL 3 |
#define | CONFIG_PLL0_SOURCE PLL_SRC_OSC0 |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 |
#define | CONFIG_USBCLK_DIV 1 |
#define | CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 |
#define CONFIG_PLL0_DIV 1 |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_MUL 3 |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0 |
Referenced by pll_enable_config_defaults().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0 |
Referenced by sysclk_init().
#define CONFIG_USBCLK_DIV 1 |
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 |