Microchip® Advanced Software Framework

Data Structures | Macros
usbc_host.h File Reference

USBC Host Driver header file.

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

#include "compiler.h"
#include "preprocessor.h"
#include "usbc_otg.h"

Data Structures

struct  sam_usbc_ctr_sta_bk_t
 
struct  sam_usbc_ctr_sta_t
 
struct  sam_usbc_pcksize_bk_t
 
struct  uhd_desc_table_t
 

Macros

#define USBC_UPSTA0CLR_PERRIC   3
 
#define USBC_UPSTA0CLR_PERRIC_MASK   0x00000008
 
#define USBC_UPSTA0CLR_PERRIC_OFFSET   3
 
#define USBC_UPSTA0CLR_PERRIC_SIZE   1
 
USBC Host IP properties

These macros give access to IP properties

Get maximal number of endpoints

#define uhd_get_pipe_max_nbr()   otg_get_max_nbr_endpoints()
 
#define UHD_MAX_PEP_NB   USBC_EPT_NBR
 
#define UHD_PEP_NB   (UHD_MAX_PEP_NB+1)
 
Host Misc

Disable all interrupts

#define uhd_disable_all_interrupts()
 
#define uhd_disable_wakeup_interrupts()
 Disable wakeup/resume interrupts. More...
 
#define uhd_ack_all_interrupts()
 Ack all interrupts. More...
 
Host Vbus line control

VBOF is an optional output pin which allows to enable or disable the external VBus generator.

VBOF is managed through GPIO driver. This feature is optional, and it is enabled if USB_VBOF_PIN is defined in board.h and (CONF_BOARD_USB_VBUS_CONTROL) not defined in conf_board.h.

#define UHD_VBUS_CTRL   (defined(CONF_BOARD_USB_VBUS_CONTROL))
 
#define UHD_VBOF_IO   (defined(USB_VBOF_PIN) && UHD_VBUS_CTRL)
 
#define pad_vbus_enable()   ioport_set_pin_level(USB_VBOF_PIN, USB_VBOF_ACTIVE_LEVEL)
 
#define pad_vbus_disable()   ioport_set_pin_level(USB_VBOF_PIN, USB_VBOF_INACTIVE_LEVEL)
 
Host Vbus line error monitoring

The VBus generator can provide an error signal through a GPIO or EIC pin.

This feature is optional, and it is enabled if USB_VBERR_PIN or USB_VBERR_EIC is defined in board.h and CONF_BOARD_USB_VBUS_ERR_DETECT defined in conf_board.h.

#define UHD_VBUS_ERR_DETECT   (defined(CONF_BOARD_USB_VBUS_ERR_DETECT))
 
#define UHD_VBERR_IO   (defined(USB_VBERR_PIN) && UHD_VBUS_ERR_DETECT)
 
#define UHD_VBERR_EIC   (defined(USB_VBERR_EIC) && UHD_VBUS_ERR_DETECT)
 
#define pad_vbus_error_init()   eic_pad_init(USB_VBERR_EIC_LINE, uhd_vberr_handler, USB_VBERR_EIC_IRQn, USB_VBERR_EIC, UHD_USB_INT_LEVEL);
 
#define pad_vbus_error_interrupt_disable()   eic_line_disable_interrupt(EIC, USB_VBERR_EIC_LINE)
 
#define pad_ack_vbus_error_interrupt()
 
#define Is_pad_vbus_error()   ioport_get_pin_level(USB_VBERR_EIC)
 
USB device connection/disconnection monitoring
#define uhd_enable_connection_int()   USBC_REG_SET(UHINTE,DCONNIE)
 
#define uhd_disable_connection_int()   USBC_REG_CLR(UHINTE,DCONNIE)
 
#define Is_uhd_connection_int_enabled()   USBC_TST_BITS(UHINTE,DCONNIE)
 
#define uhd_raise_connection()   USBC_REG_SET(UHINT,DCONNI);
 
#define uhd_ack_connection()   USBC_REG_CLR(UHINT,DCONNI)
 
#define Is_uhd_connection()   USBC_TST_BITS(UHINT,DCONNI)
 
#define uhd_enable_disconnection_int()   USBC_REG_SET(UHINTE,DDISCIE)
 
#define uhd_disable_disconnection_int()   USBC_REG_CLR(UHINTE,DDISCIE)
 
#define Is_uhd_disconnection_int_enabled()   USBC_TST_BITS(UHINTE,DDISCIE)
 
#define uhd_raise_disconnection()   USBC_REG_SET(UHINT,DDISCI);
 
#define uhd_ack_disconnection()   USBC_REG_CLR(UHINT,DDISCI)
 
#define Is_uhd_disconnection()   USBC_TST_BITS(UHINT,DDISCI)
 
USB device speed control
#define uhd_get_speed_mode()   USBC_RD_BITS(USBSTA,SPEED_Msk)
 
#define Is_uhd_low_speed_mode()   (USBC_RD_BITS(USBSTA,SPEED_Msk) == USBC_USBSTA_SPEED_LOW)
 
#define Is_uhd_full_speed_mode()   (USBC_RD_BITS(USBSTA,SPEED_Msk) == USBC_USBSTA_SPEED_FULL)
 
#define Is_uhd_high_speed_mode()   false
 
Bus events control

These macros manage the bus events: reset, SOF, resume, wakeup.

#define uhd_start_reset()   USBC_SET_BITS(UHCON,RESET)
 Initiates a reset event. More...
 
#define Is_uhd_starting_reset()   USBC_TST_BITS(UHCON,RESET)
 
#define uhd_stop_reset()   USBC_CLR_BITS(UHCON,RESET)
 
#define uhd_enable_reset_sent_interrupt()   USBC_REG_SET(UHINTE,RSTIE)
 
#define uhd_disable_reset_sent_interrupt()   USBC_REG_CLR(UHINTE,RSTIE)
 
#define Is_uhd_reset_sent_interrupt_enabled()   USBC_TST_BITS(UHINTE,RSTIE)
 
#define uhd_ack_reset_sent()   USBC_REG_CLR(UHINT,RSTI)
 
#define Is_uhd_reset_sent()   USBC_TST_BITS(UHINT,RSTI)
 
#define uhd_enable_sof()   USBC_SET_BITS(UHCON,SOFE)
 Initiates a SOF events. More...
 
#define uhd_disable_sof()   USBC_CLR_BITS(UHCON,SOFE)
 
#define Is_uhd_sof_enabled()   USBC_TST_BITS(UHCON,SOFE)
 
#define uhd_get_sof_number()   USBC_RD_BITFIELD(UHFNUM,FNUM)
 
#define uhd_get_microsof_number()
 
#define uhd_get_frame_position()   USBC_RD_BITFIELD(UHFNUM,FLENHIGH)
 
#define uhd_enable_sof_interrupt()   USBC_REG_SET(UHINTE,HSOFIE)
 
#define uhd_disable_sof_interrupt()   USBC_REG_CLR(UHINTE,HSOFIE)
 
#define Is_uhd_sof_interrupt_enabled()   USBC_TST_BITS(UHINTE,HSOFIE)
 
#define uhd_ack_sof()   USBC_REG_CLR(UHINT,HSOFI)
 
#define Is_uhd_sof()   USBC_TST_BITS(UHINT,HSOFI)
 
#define uhd_send_resume()   USBC_SET_BITS(UHCON,RESUME)
 Initiates a resume event It is called downstream resume event. More...
 
#define Is_uhd_sending_resume()   USBC_TST_BITS(UHCON,RESUME)
 
#define uhd_enable_downstream_resume_interrupt()   USBC_REG_SET(UHINTE,RSMEDIE)
 
#define uhd_disable_downstream_resume_interrupt()   USBC_REG_CLR(UHINTE,RSMEDIE)
 
#define Is_uhd_downstream_resume_interrupt_enabled()   USBC_TST_BITS(UHINTE,RSMEDIE)
 
#define uhd_ack_downstream_resume()   USBC_REG_CLR(UHINT,RSMEDI)
 
#define Is_uhd_downstream_resume()   USBC_TST_BITS(UHINT,RSMEDI)
 
#define uhd_enable_wakeup_interrupt()   USBC_REG_SET(UHINTE,HWUPIE)
 Detection of a wake-up event A wake-up event is received when the host controller is in the suspend mode: More...
 
#define uhd_disable_wakeup_interrupt()   USBC_REG_CLR(UHINTE,HWUPIE)
 
#define Is_uhd_wakeup_interrupt_enabled()   USBC_TST_BITS(UHINTE,HWUPIE)
 
#define uhd_ack_wakeup()   USBC_REG_CLR(UHINT,HWUPI)
 
#define Is_uhd_wakeup()   USBC_TST_BITS(UHINT,HWUPI)
 
#define uhd_enable_upstream_resume_interrupt()   USBC_REG_SET(UHINTE,RXRSMIE)
 
#define uhd_disable_upstream_resume_interrupt()   USBC_REG_CLR(UHINTE,RXRSMIE)
 
#define Is_uhd_upstream_resume_interrupt_enabled()   USBC_TST_BITS(UHINTE,RXRSMIE)
 
#define uhd_ack_upstream_resume()   USBC_REG_CLR(UHINT,RXRSMI)
 
#define Is_uhd_upstream_resume()   USBC_TST_BITS(UHINT,RXRSMI)
 
Pipes management
#define USBC_ARRAY(reg, index)   (((volatile uint32_t*)(&USBC->reg))[index])
 Generic macros for USBC pipe registers that can be arrayed. More...
 
#define USBC_P_CLR_BITS(reg, bit, pipe)
 
#define USBC_P_SET_BITS(reg, bit, pipe)
 
#define USBC_P_TST_BITS(reg, bit, pipe)
 
#define USBC_P_RD_BITFIELD(reg, bit, pipe)
 
#define USBC_P_WR_BITFIELD(reg, bit, pipe, value)
 
#define USBC_P_REG_CLR(reg, bit, pipe)
 
#define USBC_P_REG_SET(reg, bit, pipe)
 
#define uhd_udesc_set_uhaddr(pipe, addr)   uhd_g_pipe_table[pipe].CTR_STA.uhaddr = addr
 USB address of pipes. More...
 
#define uhd_udesc_set_uhaddr_bk1(pipe, addr)   uhd_g_pipe_table[pipe].CTR_STA1.uhaddr = addr
 
#define uhd_udesc_get_uhaddr(pipe)   uhd_g_pipe_table[pipe].CTR_STA.uhaddr
 
#define uhd_enable_pipe(p)   (Set_bits(USBC->USBC_UPRST, USBC_UPRST_PEN0 << (p)))
 Pipe enable Enable, disable, reset, freeze. More...
 
#define uhd_disable_pipe(p)   (Clr_bits(USBC->USBC_UPRST, USBC_UPRST_PEN0 << (p)))
 
#define Is_uhd_pipe_enabled(p)   (Tst_bits(USBC->USBC_UPRST, USBC_UPRST_PEN0 << (p)))
 
#define uhd_freeze_pipe(p)   USBC_P_REG_SET(UPCON,PFREEZE,p)
 
#define uhd_unfreeze_pipe(p)   USBC_P_REG_CLR(UPCON,PFREEZE,p)
 
#define Is_uhd_pipe_frozen(p)   USBC_P_TST_BITS(UPCON,PFREEZE,p)
 
#define uhd_reset_data_toggle(p)   USBC_P_REG_CLR(UPCON,INITDTGL,p)
 
#define uhd_set_data_toggle(p)   USBC_P_REG_SET(UPCON,INITDTGL,p)
 
#define uhd_set_bank0(p)   USBC_P_REG_CLR(UPCON,INITBK,p)
 
#define uhd_set_bank1(p)   USBC_P_REG_SET(UPCON,INITBK,p)
 
#define uhd_configure_pipe_binterval(p, freq)   USBC_P_WR_BITFIELD(UPCFG,BINTERVAL,p,freq)
 Pipe configuration. More...
 
#define uhd_get_pipe_binterval(p)   USBC_P_RD_BITFIELD(UPCFG,BINTERVAL,p)
 
#define uhd_udesc_set_epnum(pipe, ep)   uhd_g_pipe_table[pipe].CTR_STA.ep_num = ep
 
#define uhd_udesc_get_epnum(pipe)   uhd_g_pipe_table[pipe].CTR_STA.ep_num
 
#define uhd_configure_pipe_type(p, type)   USBC_P_WR_BITFIELD(UPCFG,PTYPE,p, type)
 
#define uhd_get_pipe_type(p)   USBC_P_RD_BITFIELD(UPCFG,PTYPE,p)
 
#define uhd_configure_pipe_token(p, token)   USBC_P_WR_BITFIELD(UPCFG,PTOKEN,p, token)
 
#define uhd_get_pipe_token(p)   USBC_P_RD_BITFIELD(UPCFG,PTOKEN,p)
 
#define uhd_is_pipe_in(p)   ((USBC_UPCFG0_PTOKEN_IN>>USBC_UPCFG0_PTOKEN_Pos)==uhd_get_pipe_token(p))
 
#define uhd_is_pipe_out(p)   ((USBC_UPCFG0_PTOKEN_OUT>>USBC_UPCFG0_PTOKEN_Pos)==uhd_get_pipe_token(p))
 
#define uhd_get_pipe_endpoint_address(p)
 
#define uhd_format_pipe_size(size)   (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
 Bounds given integer size to allowed range and rounds it up to the nearest available greater size, then applies register format of USBC controller for pipe size bit-field. More...
 
#define uhd_configure_pipe_size(p, size)   USBC_P_WR_BITFIELD(UPCFG,PSIZE,p, uhd_format_pipe_size(size))
 
#define uhd_get_pipe_size(p)   (8 << USBC_P_RD_BITFIELD(UPCFG,PSIZE,p))
 
#define uhd_configure_pipe_bank(p, bank)   USBC_P_WR_BITFIELD(UPCFG,PBK,p,bank)
 
#define uhd_get_pipe_bank(p)   USBC_P_RD_BITFIELD(UPCFG,PBK,p)
 
#define uhd_udesc_set_errormax(pipe, val)   uhd_g_pipe_table[pipe].CTR_STA.error_number_max = val
 
#define uhd_configure_pipe(p, bInterval, ep_num, type, token, size, bank)
 
#define uhd_enable_pipe_interrupt(p)   (USBC->USBC_UHINTESET = USBC_UHINTESET_P0INTES << (p))
 Pipe main interrupts management. More...
 
#define uhd_disable_pipe_interrupt(p)   (USBC->USBC_UHINTECLR = USBC_UHINTECLR_P0INTEC << (p))
 
#define Is_uhd_pipe_interrupt_enabled(p)   (Tst_bits(USBC->USBC_UHINTE, USBC_UHINTE_P0INTE << (p)))
 
#define Is_uhd_pipe_interrupt(p)   (Tst_bits(USBC->USBC_UHINT, USBC_UHINT_P0INT << (p)))
 
#define uhd_get_interrupt_pipe_number()
 returns the lowest pipe number generating a pipe interrupt or UHD_PEP_NB if none More...
 
#define USBC_UHINT_P0INT_Pos   8
 
#define USBC_UHINTE_P0INTE_Pos   8
 
#define uhd_enable_errorflow_interrupt(p)   USBC_P_REG_SET(UPCON,ERRORFIE,p)
 Pipe overflow and underflow for isochronous and interrupt endpoints. More...
 
#define uhd_disable_errorflow_interrupt(p)   USBC_P_REG_CLR(UPCON,ERRORFIE,p)
 
#define Is_uhd_errorflow_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,ERRORFIE,p)
 
#define uhd_ack_errorflow_interrupt(p)   USBC_P_REG_CLR(UPSTA,ERRORFI,p)
 
#define Is_uhd_errorflow(p)   USBC_P_TST_BITS(UPSTA,ERRORFI,p)
 
#define uhd_enable_stall_interrupt(p)   USBC_P_REG_SET(UPCON,RXSTALLDE,p)
 USB packet errors management. More...
 
#define uhd_disable_stall_interrupt(p)   USBC_P_REG_CLR(UPCON,RXSTALLDE,p)
 
#define Is_uhd_stall_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,RXSTALLDE,p)
 
#define uhd_ack_stall(p)   USBC_P_REG_CLR(UPSTA,RXSTALLDI,p)
 
#define Is_uhd_stall(p)   USBC_P_TST_BITS(UPSTA,RXSTALLDI,p)
 
#define uhd_enable_crc_error_interrupt(p)   USBC_P_REG_SET(UPCON,RXSTALLDE,p)
 
#define uhd_disable_crc_error_interrupt(p)   USBC_P_REG_CLR(UPCON,RXSTALLDE,p)
 
#define Is_uhd_crc_error_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,RXSTALLDE,p)
 
#define uhd_ack_crc_error(p)   USBC_P_REG_CLR(UPSTA,RXSTALLDI,p)
 
#define Is_uhd_crc_error(p)   USBC_P_TST_BITS(UPSTA,RXSTALLDI,p)
 
#define uhd_enable_pipe_error_interrupt(p)   USBC_P_REG_SET(UPCON,PERRE,p)
 
#define uhd_disable_pipe_error_interrupt(p)   USBC_P_REG_CLR(UPCON,PERRE,p)
 
#define Is_uhd_pipe_error_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,PERRE,p)
 
#define uhd_ack_pipe_error(p)   USBC_P_REG_CLR(UPSTA,PERRI,p)
 
#define Is_uhd_pipe_error(p)   USBC_P_TST_BITS(UPSTA,PERRI,p)
 
#define uhd_raise_pipe_error(p)   USBC_P_REG_SET(UPSTA,PERRI,p)
 
#define USBC_UPERR_UPERR0_DATATGL_MASK   (1<<0)
 
#define USBC_UPERR_UPERR0_DATAPID_MASK   (1<<1)
 
#define USBC_UPERR_UPERR0_PID_MASK   (1<<2)
 
#define USBC_UPERR_UPERR0_TIMEOUT_MASK   (1<<3)
 
#define USBC_UPERR_UPERR0_CRC16_MASK   (1<<4)
 
#define uhd_udesc_get_error_status(pipe)   uhd_g_pipe_table[pipe].CTR_STA.error_status
 
#define uhd_udesc_ack_error_status(pipe)   uhd_g_pipe_table[pipe].CTR_STA.error_status = 0
 
#define uhd_data_toggle(p)   USBC_P_RD_BITFIELD(UPSTA,DTSEQ,p)
 Pipe data management. More...
 
#define uhd_enable_bank_interrupt(p)   USBC_P_REG_SET(UPCON,NBUSYBKE,p)
 
#define uhd_disable_bank_interrupt(p)   USBC_P_REG_CLR(UPCON,NBUSYBKE,p)
 
#define Is_uhd_bank_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,NBUSYBKE,p)
 
#define uhd_nb_busy_bank(p)   USBC_P_RD_BITFIELD(UPSTA,NBUSYBK,p)
 
#define uhd_current_bank(p)   USBC_P_RD_BITFIELD(UPSTA,CURRBK,p)
 
#define uhd_udesc_set_buf0_addr(pipe, buf)   uhd_g_pipe_table[pipe].pipe_add_bank0 = buf
 
#define uhd_udesc_rst_buf0_size(pipe)   uhd_g_pipe_table[pipe].PCKSIZE_BK0.multi_packet_size = 0
 
#define uhd_udesc_get_buf0_size(pipe)   uhd_g_pipe_table[pipe].PCKSIZE_BK0.multi_packet_size
 
#define uhd_udesc_set_buf0_size(pipe, size)   uhd_g_pipe_table[pipe].PCKSIZE_BK0.multi_packet_size = size
 
#define uhd_udesc_rst_buf0_ctn(pipe)   uhd_g_pipe_table[pipe].PCKSIZE_BK0.byte_count = 0
 
#define uhd_udesc_get_buf0_ctn(pipe)   uhd_g_pipe_table[pipe].PCKSIZE_BK0.byte_count
 
#define uhd_udesc_set_buf0_ctn(pipe, size)   uhd_g_pipe_table[pipe].PCKSIZE_BK0.byte_count = size
 
#define uhd_udesc_set_buf0_autozlp(pipe, val)   uhd_g_pipe_table[pipe].PCKSIZE_BK0.auto_zlp = val
 
#define UHD_ENDPOINT_MAX_TRANS   ((32*1024)-1)
 
#define uhd_enable_ram_eccess_error_interrupt(p)   USBC_P_REG_SET(UPCON,RAMACERIE,p)
 
#define uhd_disable_ram_eccess_error_interrupt(p)   USBC_P_REG_CLR(UPCON,RAMACERIE,p)
 
#define Is_uhd_ram_eccess_error_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,RAMACERIE,p)
 
#define uhd_ack_ram_eccess_error(p)   USBC_P_REG_CLR(UPSTA,RAMACERI,p)
 
#define Is_uhd_ram_eccess_error(p)   USBC_P_TST_BITS(UPSTA,RAMACERI,p)
 
#define Is_uhd_fifocon(p)   USBC_P_TST_BITS(UPCON,FIFOCON,p)
 
#define uhd_ack_fifocon(p)   USBC_P_REG_CLR(UPCON,FIFOCON,p)
 
#define uhd_enable_setup_ready_interrupt(p)   USBC_P_REG_SET(UPCON,TXSTPE,p)
 
#define uhd_disable_setup_ready_interrupt(p)   USBC_P_REG_CLR(UPCON,TXSTPE,p)
 
#define Is_uhd_setup_ready_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,TXSTPE,p)
 
#define uhd_ack_setup_ready(p)   USBC_P_REG_CLR(UPSTA,TXSTPI,p)
 
#define Is_uhd_setup_ready(p)   USBC_P_TST_BITS(UPSTA,TXSTPI,p)
 
#define uhd_enable_in_received_interrupt(p)   USBC_P_REG_SET(UPCON,RXINE,p)
 
#define uhd_disable_in_received_interrupt(p)   USBC_P_REG_CLR(UPCON,RXINE,p)
 
#define Is_uhd_in_received_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,RXINE,p)
 
#define uhd_ack_in_received(p)   USBC_P_REG_CLR(UPSTA,RXINI,p)
 
#define Is_uhd_in_received(p)   USBC_P_TST_BITS(UPSTA,RXINI,p)
 
#define uhd_enable_out_ready_interrupt(p)   USBC_P_REG_SET(UPCON,TXOUTE,p)
 
#define uhd_disable_out_ready_interrupt(p)   USBC_P_REG_CLR(UPCON,TXOUTE,p)
 
#define Is_uhd_out_ready_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,TXOUTE,p)
 
#define uhd_ack_out_ready(p)   USBC_P_REG_CLR(UPSTA,TXOUTI,p)
 
#define Is_uhd_out_ready(p)   USBC_P_TST_BITS(UPSTA,TXOUTI,p)
 
#define uhd_raise_out_ready(p)   USBC_P_REG_SET(UPSTA,TXOUTI,p)
 
#define uhd_enable_nak_received_interrupt(p)   USBC_P_REG_SET(UPCON,NAKEDE,p)
 
#define uhd_disable_nak_received_interrupt(p)   USBC_P_REG_CLR(UPCON,NAKEDE,p)
 
#define Is_uhd_nak_received_interrupt_enabled(p)   USBC_P_TST_BITS(UPCON,NAKEDE,p)
 
#define uhd_ack_nak_received(p)   USBC_P_REG_CLR(UPSTA,NAKEDI,p)
 
#define Is_uhd_nak_received(p)   USBC_P_TST_BITS(UPSTA,NAKEDI,p)
 
#define uhd_enable_continuous_in_mode(p)   USBC_P_SET_BITS(UPINRQ,INMODE,p)
 
#define uhd_disable_continuous_in_mode(p)   USBC_P_CLR_BITS(UPINRQ,INMODE,p)
 
#define Is_uhd_continuous_in_mode_enabled(p)   USBC_P_TST_BITS(UPINRQ,INMODE,p)
 
#define uhd_in_request_number(p, in_num)   USBC_P_WR_BITFIELD(UPINRQ,INRQ,p,in_num)
 
#define uhd_get_in_request_number(p)   USBC_P_RD_BITFIELD(UPINRQ,INRQ,p)
 
#define uhd_get_pipe_fifo_access(p, scale)   (((volatile TPASTE3(uint, scale, _t) (*)[0x10000 / ((scale) / 8)])SAM_USBC_SLAVE)[(p)])
 Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected pipe. More...
 

#define Is_uhd_bank_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,NBUSYBKE,p)
#define Is_uhd_continuous_in_mode_enabled (   p)    USBC_P_TST_BITS(UPINRQ,INMODE,p)
#define Is_uhd_crc_error (   p)    USBC_P_TST_BITS(UPSTA,RXSTALLDI,p)
#define Is_uhd_crc_error_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,RXSTALLDE,p)
#define Is_uhd_errorflow (   p)    USBC_P_TST_BITS(UPSTA,ERRORFI,p)
#define Is_uhd_errorflow_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,ERRORFIE,p)
#define Is_uhd_fifocon (   p)    USBC_P_TST_BITS(UPCON,FIFOCON,p)
#define Is_uhd_in_received (   p)    USBC_P_TST_BITS(UPSTA,RXINI,p)

Referenced by uhd_ctrl_interrupt(), and uhd_pipe_interrupt().

#define Is_uhd_in_received_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,RXINE,p)
#define Is_uhd_nak_received (   p)    USBC_P_TST_BITS(UPSTA,NAKEDI,p)
#define Is_uhd_nak_received_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,NAKEDE,p)
#define Is_uhd_out_ready (   p)    USBC_P_TST_BITS(UPSTA,TXOUTI,p)

Referenced by uhd_ctrl_interrupt(), and uhd_pipe_interrupt().

#define Is_uhd_out_ready_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,TXOUTE,p)
#define Is_uhd_pipe_enabled (   p)    (Tst_bits(USBC->USBC_UPRST, USBC_UPRST_PEN0 << (p)))

Referenced by uhd_ctrl_phase_setup(), uhd_ep0_alloc(), uhd_ep_alloc(), and uhd_get_pipe().

#define Is_uhd_pipe_error (   p)    USBC_P_TST_BITS(UPSTA,PERRI,p)

Referenced by uhd_ctrl_interrupt(), and uhd_pipe_interrupt().

#define Is_uhd_pipe_error_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,PERRE,p)
#define Is_uhd_pipe_frozen (   p)    USBC_P_TST_BITS(UPCON,PFREEZE,p)

Referenced by uhd_ctrl_interrupt(), uhd_pipe_interrupt(), uhd_pipe_trans_complet(), and uhd_suspend().

#define Is_uhd_pipe_interrupt (   p)    (Tst_bits(USBC->USBC_UHINT, USBC_UHINT_P0INT << (p)))
#define Is_uhd_pipe_interrupt_enabled (   p)    (Tst_bits(USBC->USBC_UHINTE, USBC_UHINTE_P0INTE << (p)))
#define Is_uhd_ram_eccess_error (   p)    USBC_P_TST_BITS(UPSTA,RAMACERI,p)
#define Is_uhd_ram_eccess_error_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,RAMACERIE,p)
#define Is_uhd_setup_ready (   p)    USBC_P_TST_BITS(UPSTA,TXSTPI,p)

Referenced by uhd_ctrl_interrupt().

#define Is_uhd_setup_ready_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,TXSTPE,p)
#define Is_uhd_stall (   p)    USBC_P_TST_BITS(UPSTA,RXSTALLDI,p)

Referenced by uhd_ctrl_interrupt(), and uhd_pipe_interrupt().

#define Is_uhd_stall_interrupt_enabled (   p)    USBC_P_TST_BITS(UPCON,RXSTALLDE,p)
#define uhd_ack_crc_error (   p)    USBC_P_REG_CLR(UPSTA,RXSTALLDI,p)
#define uhd_ack_errorflow_interrupt (   p)    USBC_P_REG_CLR(UPSTA,ERRORFI,p)
#define uhd_ack_fifocon (   p)    USBC_P_REG_CLR(UPCON,FIFOCON,p)

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_data_out(), uhd_ctrl_phase_setup(), uhd_ctrl_phase_zlp_in(), uhd_ctrl_phase_zlp_out(), and uhd_pipe_trans_complet().

#define uhd_ack_in_received (   p)    USBC_P_REG_CLR(UPSTA,RXINI,p)

Referenced by uhd_ctrl_interrupt(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_zlp_in(), and uhd_pipe_interrupt().

#define uhd_ack_nak_received (   p)    USBC_P_REG_CLR(UPSTA,NAKEDI,p)
#define uhd_ack_out_ready (   p)    USBC_P_REG_CLR(UPSTA,TXOUTI,p)

Referenced by uhd_ctrl_interrupt(), uhd_ctrl_phase_data_out(), uhd_ctrl_phase_zlp_out(), uhd_ep_alloc(), and uhd_pipe_interrupt().

#define uhd_ack_pipe_error (   p)    USBC_P_REG_CLR(UPSTA,PERRI,p)

Referenced by uhd_ctrl_interrupt(), uhd_pipe_get_error(), and uhd_pipe_interrupt().

#define uhd_ack_ram_eccess_error (   p)    USBC_P_REG_CLR(UPSTA,RAMACERI,p)
#define uhd_ack_setup_ready (   p)    USBC_P_REG_CLR(UPSTA,TXSTPI,p)

Referenced by uhd_ctrl_interrupt(), and uhd_ctrl_phase_setup().

#define uhd_ack_stall (   p)    USBC_P_REG_CLR(UPSTA,RXSTALLDI,p)

Referenced by uhd_ctrl_interrupt(), and uhd_pipe_interrupt().

#define uhd_configure_pipe (   p,
  bInterval,
  ep_num,
  type,
  token,
  size,
  bank 
)
Value:
{ \
USBC_ARRAY(USBC_UPCFG0,p) = \
(((uint32_t)(bInterval) << USBC_UPCFG0_BINTERVAL_Pos) & USBC_UPCFG0_BINTERVAL_Msk) |\
(((uint32_t)(type ) << USBC_UPCFG0_PTYPE_Pos ) & USBC_UPCFG0_PTYPE_Msk ) |\
(((uint32_t)(token ) << USBC_UPCFG0_PTOKEN_Pos) & USBC_UPCFG0_PTOKEN_Msk) |\
((uint32_t)uhd_format_pipe_size(size) << USBC_UPCFG0_PSIZE_Pos ) |\
(((uint32_t)(bank ) << USBC_UPCFG0_PBK_Pos ) & USBC_UPCFG0_PBK_Msk ); \
uhd_udesc_set_epnum(p,ep_num); \
uhd_udesc_set_errormax(p,3); \
}
uhd_udesc_set_errormax
#define uhd_udesc_set_errormax(pipe, val)
Definition: usbc_host.h:333
uhd_format_pipe_size
#define uhd_format_pipe_size(size)
Bounds given integer size to allowed range and rounds it up to the nearest available greater size...
Definition: usbc_host.h:325
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
uhd_udesc_set_epnum
#define uhd_udesc_set_epnum(pipe, ep)
Definition: usbc_host.h:305

Referenced by uhd_ep0_alloc(), and uhd_ep_alloc().

#define uhd_configure_pipe_bank (   p,
  bank 
)    USBC_P_WR_BITFIELD(UPCFG,PBK,p,bank)
#define uhd_configure_pipe_binterval (   p,
  freq 
)    USBC_P_WR_BITFIELD(UPCFG,BINTERVAL,p,freq)

Pipe configuration.

#define uhd_configure_pipe_size (   p,
  size 
)    USBC_P_WR_BITFIELD(UPCFG,PSIZE,p, uhd_format_pipe_size(size))
#define uhd_configure_pipe_token (   p,
  token 
)    USBC_P_WR_BITFIELD(UPCFG,PTOKEN,p, token)

Referenced by uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_data_out(), uhd_ctrl_phase_setup(), uhd_ctrl_phase_zlp_in(), and uhd_ctrl_phase_zlp_out().

#define uhd_configure_pipe_type (   p,
  type 
)    USBC_P_WR_BITFIELD(UPCFG,PTYPE,p, type)
#define uhd_current_bank (   p)    USBC_P_RD_BITFIELD(UPSTA,CURRBK,p)
#define uhd_data_toggle (   p)    USBC_P_RD_BITFIELD(UPSTA,DTSEQ,p)

Pipe data management.

Referenced by uhd_ep_abort_pipe().

#define uhd_disable_bank_interrupt (   p)    USBC_P_REG_CLR(UPCON,NBUSYBKE,p)
#define uhd_disable_continuous_in_mode (   p)    USBC_P_CLR_BITS(UPINRQ,INMODE,p)

Referenced by uhd_pipe_trans_complet().

#define uhd_disable_crc_error_interrupt (   p)    USBC_P_REG_CLR(UPCON,RXSTALLDE,p)
#define uhd_disable_errorflow_interrupt (   p)    USBC_P_REG_CLR(UPCON,ERRORFIE,p)
#define uhd_disable_in_received_interrupt (   p)    USBC_P_REG_CLR(UPCON,RXINE,p)
#define uhd_disable_nak_received_interrupt (   p)    USBC_P_REG_CLR(UPCON,NAKEDE,p)
#define uhd_disable_out_ready_interrupt (   p)    USBC_P_REG_CLR(UPCON,TXOUTE,p)
#define uhd_disable_pipe (   p)    (Clr_bits(USBC->USBC_UPRST, USBC_UPRST_PEN0 << (p)))

Referenced by uhd_ep_abort_pipe(), and uhd_ep_free().

#define uhd_disable_pipe_error_interrupt (   p)    USBC_P_REG_CLR(UPCON,PERRE,p)
#define uhd_disable_pipe_interrupt (   p)    (USBC->USBC_UHINTECLR = USBC_UHINTECLR_P0INTEC << (p))

Referenced by uhd_pipe_interrupt().

#define uhd_disable_ram_eccess_error_interrupt (   p)    USBC_P_REG_CLR(UPCON,RAMACERIE,p)
#define uhd_disable_setup_ready_interrupt (   p)    USBC_P_REG_CLR(UPCON,TXSTPE,p)
#define uhd_disable_stall_interrupt (   p)    USBC_P_REG_CLR(UPCON,RXSTALLDE,p)
#define uhd_enable_bank_interrupt (   p)    USBC_P_REG_SET(UPCON,NBUSYBKE,p)
#define uhd_enable_continuous_in_mode (   p)    USBC_P_SET_BITS(UPINRQ,INMODE,p)

Referenced by uhd_pipe_trans_complet().

#define uhd_enable_crc_error_interrupt (   p)    USBC_P_REG_SET(UPCON,RXSTALLDE,p)
#define uhd_enable_errorflow_interrupt (   p)    USBC_P_REG_SET(UPCON,ERRORFIE,p)

Pipe overflow and underflow for isochronous and interrupt endpoints.

#define uhd_enable_in_received_interrupt (   p)    USBC_P_REG_SET(UPCON,RXINE,p)

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_zlp_in(), and uhd_pipe_trans_complet().

#define uhd_enable_nak_received_interrupt (   p)    USBC_P_REG_SET(UPCON,NAKEDE,p)
#define uhd_enable_out_ready_interrupt (   p)    USBC_P_REG_SET(UPCON,TXOUTE,p)

Referenced by uhd_ctrl_phase_data_out(), uhd_pipe_trans_complet(), and uhd_sof_interrupt().

#define uhd_enable_pipe (   p)    (Set_bits(USBC->USBC_UPRST, USBC_UPRST_PEN0 << (p)))

Pipe enable Enable, disable, reset, freeze.

Referenced by uhd_ep0_alloc(), uhd_ep_abort_pipe(), and uhd_ep_alloc().

#define uhd_enable_pipe_error_interrupt (   p)    USBC_P_REG_SET(UPCON,PERRE,p)

Referenced by uhd_ep0_alloc(), uhd_ep_abort_pipe(), and uhd_ep_alloc().

#define uhd_enable_pipe_interrupt (   p)    (USBC->USBC_UHINTESET = USBC_UHINTESET_P0INTES << (p))

Pipe main interrupts management.

Referenced by uhd_ep0_alloc(), uhd_ep_alloc(), and uhd_pipe_trans_complet().

#define uhd_enable_ram_eccess_error_interrupt (   p)    USBC_P_REG_SET(UPCON,RAMACERIE,p)
#define uhd_enable_setup_ready_interrupt (   p)    USBC_P_REG_SET(UPCON,TXSTPE,p)

Referenced by uhd_ctrl_phase_setup().

#define uhd_enable_stall_interrupt (   p)    USBC_P_REG_SET(UPCON,RXSTALLDE,p)

USB packet errors management.

Referenced by uhd_ep0_alloc(), uhd_ep_abort_pipe(), and uhd_ep_alloc().

#define UHD_ENDPOINT_MAX_TRANS   ((32*1024)-1)

Referenced by uhd_pipe_trans_complet().

#define uhd_format_pipe_size (   size)    (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)

Bounds given integer size to allowed range and rounds it up to the nearest available greater size, then applies register format of USBC controller for pipe size bit-field.

#define uhd_freeze_pipe (   p)    USBC_P_REG_SET(UPCON,PFREEZE,p)

Referenced by uhd_ctrl_interrupt(), uhd_ep_abort_pipe(), uhd_pipe_interrupt(), uhd_pipe_trans_complet(), uhd_sof_interrupt(), and uhd_suspend().

#define uhd_get_in_request_number (   p)    USBC_P_RD_BITFIELD(UPINRQ,INRQ,p)

Referenced by uhd_pipe_trans_complet().

#define uhd_get_interrupt_pipe_number ( )
Value:
(ctz(((USBC->USBC_UHINT >> USBC_UHINT_P0INT_Pos) & \
(USBC->USBC_UHINTE >> USBC_UHINTE_P0INTE_Pos)) | (1 << UHD_PEP_NB)))
USBC_UHINT_P0INT_Pos
#define USBC_UHINT_P0INT_Pos
Definition: usbc_host.h:362
UHD_PEP_NB
#define UHD_PEP_NB
Definition: usbc_host.h:65
ctz
#define ctz(u)
Counts the trailing zero bits of the given value considered as a 32-bit integer.
Definition: compiler.h:621
USBC_UHINTE_P0INTE_Pos
#define USBC_UHINTE_P0INTE_Pos
Definition: usbc_host.h:363

returns the lowest pipe number generating a pipe interrupt or UHD_PEP_NB if none

Referenced by uhd_interrupt().

#define uhd_get_pipe_bank (   p)    USBC_P_RD_BITFIELD(UPCFG,PBK,p)
#define uhd_get_pipe_binterval (   p)    USBC_P_RD_BITFIELD(UPCFG,BINTERVAL,p)
#define uhd_get_pipe_endpoint_address (   p)
Value:
(uhd_udesc_get_epnum(p) \
| (uhd_is_pipe_in(p)? USB_EP_DIR_IN : USB_EP_DIR_OUT))
uhd_udesc_get_epnum
#define uhd_udesc_get_epnum(pipe)
Definition: usbc_host.h:307
USB_EP_DIR_OUT
#define USB_EP_DIR_OUT
Endpoint transfer direction is OUT.
Definition: usb_protocol.h:279
USB_EP_DIR_IN
#define USB_EP_DIR_IN
Endpoint transfer direction is IN.
Definition: usb_protocol.h:274
uhd_is_pipe_in
#define uhd_is_pipe_in(p)
Definition: usbc_host.h:315

Referenced by uhd_ep_free(), uhd_get_pipe(), and uhd_pipe_finish_job().

#define uhd_get_pipe_fifo_access (   p,
  scale 
)    (((volatile TPASTE3(uint, scale, _t) (*)[0x10000 / ((scale) / 8)])SAM_USBC_SLAVE)[(p)])

Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected pipe.

Parameters
pTarget Pipe number
scaleData scale in bits: 64, 32, 16 or 8
Returns
Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register
Warning
It is up to the user of this macro to make sure that all accesses are aligned with their natural boundaries except 64-bit accesses which require only 32-bit alignment.
It is up to the user of this macro to make sure that used HSB addresses are identical to the DPRAM internal pointer modulo 32 bits.
#define uhd_get_pipe_size (   p)    (8 << USBC_P_RD_BITFIELD(UPCFG,PSIZE,p))

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_data_out(), and uhd_pipe_trans_complet().

#define uhd_get_pipe_token (   p)    USBC_P_RD_BITFIELD(UPCFG,PTOKEN,p)
#define uhd_get_pipe_type (   p)    USBC_P_RD_BITFIELD(UPCFG,PTYPE,p)

Referenced by uhd_pipe_trans_complet().

#define uhd_in_request_number (   p,
  in_num 
)    USBC_P_WR_BITFIELD(UPINRQ,INRQ,p,in_num)

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_zlp_in(), and uhd_pipe_trans_complet().

#define uhd_is_pipe_in (   p)    ((USBC_UPCFG0_PTOKEN_IN>>USBC_UPCFG0_PTOKEN_Pos)==uhd_get_pipe_token(p))
#define uhd_is_pipe_out (   p)    ((USBC_UPCFG0_PTOKEN_OUT>>USBC_UPCFG0_PTOKEN_Pos)==uhd_get_pipe_token(p))

Referenced by uhd_ep_abort_pipe(), and uhd_pipe_trans_complet().

#define uhd_nb_busy_bank (   p)    USBC_P_RD_BITFIELD(UPSTA,NBUSYBK,p)
#define uhd_raise_out_ready (   p)    USBC_P_REG_SET(UPSTA,TXOUTI,p)
#define uhd_raise_pipe_error (   p)    USBC_P_REG_SET(UPSTA,PERRI,p)

Referenced by uhd_sof_interrupt().

#define uhd_reset_data_toggle (   p)    USBC_P_REG_CLR(UPCON,INITDTGL,p)

Referenced by uhd_pipe_interrupt().

#define uhd_set_bank0 (   p)    USBC_P_REG_CLR(UPCON,INITBK,p)
#define uhd_set_bank1 (   p)    USBC_P_REG_SET(UPCON,INITBK,p)
#define uhd_set_data_toggle (   p)    USBC_P_REG_SET(UPCON,INITDTGL,p)

Referenced by uhd_ep_abort_pipe().

#define uhd_udesc_ack_error_status (   pipe)    uhd_g_pipe_table[pipe].CTR_STA.error_status = 0

Referenced by uhd_pipe_get_error().

#define uhd_udesc_get_buf0_ctn (   pipe)    uhd_g_pipe_table[pipe].PCKSIZE_BK0.byte_count

Referenced by uhd_ctrl_phase_data_in(), uhd_ep_abort_pipe(), and uhd_pipe_trans_complet().

#define uhd_udesc_get_buf0_size (   pipe)    uhd_g_pipe_table[pipe].PCKSIZE_BK0.multi_packet_size

Referenced by uhd_ep_abort_pipe(), and uhd_pipe_trans_complet().

#define uhd_udesc_get_epnum (   pipe)    uhd_g_pipe_table[pipe].CTR_STA.ep_num

Referenced by uhd_ep_free().

#define uhd_udesc_get_error_status (   pipe)    uhd_g_pipe_table[pipe].CTR_STA.error_status

Referenced by uhd_pipe_get_error().

#define uhd_udesc_get_uhaddr (   pipe)    uhd_g_pipe_table[pipe].CTR_STA.uhaddr

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_out(), uhd_ctrl_phase_setup(), uhd_ctrl_request_end(), uhd_ep_free(), uhd_get_pipe(), and uhd_pipe_finish_job().

#define uhd_udesc_rst_buf0_ctn (   pipe)    uhd_g_pipe_table[pipe].PCKSIZE_BK0.byte_count = 0

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_zlp_in(), uhd_ep_run(), and uhd_pipe_trans_complet().

#define uhd_udesc_rst_buf0_size (   pipe)    uhd_g_pipe_table[pipe].PCKSIZE_BK0.multi_packet_size = 0

Referenced by uhd_ctrl_phase_data_out(), uhd_ctrl_phase_setup(), uhd_ctrl_phase_zlp_out(), uhd_ep_run(), and uhd_pipe_trans_complet().

#define uhd_udesc_set_buf0_addr (   pipe,
  buf 
)    uhd_g_pipe_table[pipe].pipe_add_bank0 = buf

Referenced by uhd_ep0_alloc(), and uhd_pipe_trans_complet().

#define uhd_udesc_set_buf0_autozlp (   pipe,
  val 
)    uhd_g_pipe_table[pipe].PCKSIZE_BK0.auto_zlp = val

Referenced by uhd_pipe_trans_complet().

#define uhd_udesc_set_buf0_ctn (   pipe,
  size 
)    uhd_g_pipe_table[pipe].PCKSIZE_BK0.byte_count = size

Referenced by uhd_ctrl_phase_data_out(), uhd_ctrl_phase_setup(), uhd_ctrl_phase_zlp_out(), and uhd_pipe_trans_complet().

#define uhd_udesc_set_buf0_size (   pipe,
  size 
)    uhd_g_pipe_table[pipe].PCKSIZE_BK0.multi_packet_size = size

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_zlp_in(), and uhd_pipe_trans_complet().

#define uhd_udesc_set_epnum (   pipe,
  ep 
)    uhd_g_pipe_table[pipe].CTR_STA.ep_num = ep
#define uhd_udesc_set_errormax (   pipe,
  val 
)    uhd_g_pipe_table[pipe].CTR_STA.error_number_max = val
#define uhd_udesc_set_uhaddr (   pipe,
  addr 
)    uhd_g_pipe_table[pipe].CTR_STA.uhaddr = addr

USB address of pipes.

Referenced by uhd_ctrl_phase_setup(), uhd_ep0_alloc(), and uhd_ep_alloc().

#define uhd_udesc_set_uhaddr_bk1 (   pipe,
  addr 
)    uhd_g_pipe_table[pipe].CTR_STA1.uhaddr = addr
#define uhd_unfreeze_pipe (   p)    USBC_P_REG_CLR(UPCON,PFREEZE,p)

Referenced by uhd_ctrl_phase_data_in(), uhd_ctrl_phase_data_in_start(), uhd_ctrl_phase_data_out(), uhd_ctrl_phase_setup(), uhd_ctrl_phase_zlp_in(), uhd_pipe_trans_complet(), and uhd_sof_interrupt().

#define USBC_ARRAY (   reg,
  index 
)    (((volatile uint32_t*)(&USBC->reg))[index])

Generic macros for USBC pipe registers that can be arrayed.

Referenced by uhd_ep_abort_pipe().

#define USBC_P_CLR_BITS (   reg,
  bit,
  pipe 
)
Value:
(Clr_bits(USBC_ARRAY(TPASTE3(USBC_,reg,0),pipe),\
TPASTE4(USBC_,reg,0_,bit)))
Clr_bits
#define Clr_bits(lvalue, mask)
Clears the bits of a C lvalue specified by a given bit-mask.
Definition: compiler.h:512
TPASTE4
#define TPASTE4(a, b, c, d)
Definition: tpaste.h:61
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
TPASTE3
#define TPASTE3(a, b, c)
Definition: tpaste.h:60
#define USBC_P_RD_BITFIELD (   reg,
  bit,
  pipe 
)
Value:
(Rd_bitfield(USBC_ARRAY(TPASTE3(USBC_,reg,0),pipe),\
TPASTE5(USBC_,reg,0_,bit,_Msk)))
Rd_bitfield
#define Rd_bitfield(value, mask)
Reads the bit-field of a value specified by a given bit-mask.
Definition: compiler.h:539
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
TPASTE5
#define TPASTE5(a, b, c, d, e)
Definition: tpaste.h:62
TPASTE3
#define TPASTE3(a, b, c)
Definition: tpaste.h:60
#define USBC_P_REG_CLR (   reg,
  bit,
  pipe 
)
Value:
(USBC_ARRAY(TPASTE3(USBC_,reg,0CLR),pipe) \
= TPASTE4(USBC_,reg,0_,bit))
TPASTE4
#define TPASTE4(a, b, c, d)
Definition: tpaste.h:61
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
TPASTE3
#define TPASTE3(a, b, c)
Definition: tpaste.h:60
#define USBC_P_REG_SET (   reg,
  bit,
  pipe 
)
Value:
(USBC_ARRAY(TPASTE3(USBC_,reg,0SET),pipe) \
= TPASTE4(USBC_,reg,0_,bit))
TPASTE4
#define TPASTE4(a, b, c, d)
Definition: tpaste.h:61
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
TPASTE3
#define TPASTE3(a, b, c)
Definition: tpaste.h:60
#define USBC_P_SET_BITS (   reg,
  bit,
  pipe 
)
Value:
(Set_bits(USBC_ARRAY(TPASTE3(USBC_,reg,0),pipe),\
TPASTE4(USBC_,reg,0_,bit)))
TPASTE4
#define TPASTE4(a, b, c, d)
Definition: tpaste.h:61
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
TPASTE3
#define TPASTE3(a, b, c)
Definition: tpaste.h:60
Set_bits
#define Set_bits(lvalue, mask)
Sets the bits of a C lvalue specified by a given bit-mask.
Definition: compiler.h:521
#define USBC_P_TST_BITS (   reg,
  bit,
  pipe 
)
Value:
(Tst_bits(USBC_ARRAY(TPASTE3(USBC_,reg,0),pipe),\
TPASTE4(USBC_,reg,0_,bit)))
Tst_bits
#define Tst_bits(value, mask)
Tests the bits of a value specified by a given bit-mask.
Definition: compiler.h:503
TPASTE4
#define TPASTE4(a, b, c, d)
Definition: tpaste.h:61
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
TPASTE3
#define TPASTE3(a, b, c)
Definition: tpaste.h:60
#define USBC_P_WR_BITFIELD (   reg,
  bit,
  pipe,
  value 
)
Value:
(Wr_bitfield(USBC_ARRAY(TPASTE3(USBC_,reg,0),pipe),\
TPASTE5(USBC_,reg,0_,bit,_Msk), value))
USBC_ARRAY
#define USBC_ARRAY(reg, index)
Generic macros for USBC pipe registers that can be arrayed.
Definition: usbc_host.h:245
TPASTE5
#define TPASTE5(a, b, c, d, e)
Definition: tpaste.h:62
TPASTE3
#define TPASTE3(a, b, c)
Definition: tpaste.h:60
Wr_bitfield
#define Wr_bitfield(lvalue, mask, bitfield)
Writes the bit-field of a C lvalue specified by a given bit-mask.
Definition: compiler.h:549
#define USBC_UHINT_P0INT_Pos   8
#define USBC_UHINTE_P0INTE_Pos   8
#define USBC_UPERR_UPERR0_CRC16_MASK   (1<<4)

Referenced by uhd_pipe_get_error().

#define USBC_UPERR_UPERR0_DATAPID_MASK   (1<<1)

Referenced by uhd_pipe_get_error().

#define USBC_UPERR_UPERR0_DATATGL_MASK   (1<<0)

Referenced by uhd_pipe_get_error().

#define USBC_UPERR_UPERR0_PID_MASK   (1<<2)

Referenced by uhd_pipe_get_error().

#define USBC_UPERR_UPERR0_TIMEOUT_MASK   (1<<3)

Referenced by uhd_pipe_get_error().

#define USBC_UPSTA0CLR_PERRIC   3
#define USBC_UPSTA0CLR_PERRIC_MASK   0x00000008
#define USBC_UPSTA0CLR_PERRIC_OFFSET   3
#define USBC_UPSTA0CLR_PERRIC_SIZE   1
Generated on Sat Mar 5 2022 00:59:05 for USB Dual Role (Device and Host) HID mouse for SAM4L Xplained Pro by   doxygen 1.8.5