This group contains functions and definitions related to configuring and enabling/disabling on-chip PLLs.

A PLL will take an input signal (the source), optionally divide the frequency by a configurable divider, and then multiply the frequency by a configurable multiplier.

Some devices don't support input dividers; specifying any other divisor than 1 on these devices will result in an assertion failure. Other devices may have various restrictions to the frequency range of the input and output signals.

Example: Setting up PLL0 with default parameters

The following example shows how to configure and enable PLL0 using the default parameters specified using the configuration symbols listed above.

pll_enable_config_defaults(0);

To configure, enable PLL0 using the default parameters and to disable a specific feature like Wide Bandwidth Mode (a UC3A3-specific PLL option.), you can use this initialization process.

struct pll_config pllcfg;
if (pll_is_locked(pll_id)) {
   return; // Pll already running
}
pll_enable_source(CONFIG_PLL0_SOURCE);
pll_config_defaults(&pllcfg, 0);
pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
pll_enable(&pllcfg, 0);
pll_wait_for_lock(0); 

When the last function call returns, PLL0 is ready to be used as the main system clock source.

Configuration Symbols

Each PLL has a set of default parameters determined by the following configuration symbols in the application's configuration file:

CONFIG_PLLn_SOURCE: The default clock source connected to the input of PLL n. Must be one of the values defined by the pll_source enum.
CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL n.
CONFIG_PLLn_DIV: The default input divider of PLL n.

These configuration symbols determine the result of calling pll_config_defaults() and pll_get_default_rate().

Data Structures
struct	pll_config
	Hardware-specific representation of PLL configuration. More...

Macros
#define	CONFIG_PLL1_DIV 0

#define	CONFIG_PLL1_MUL 0

#define	CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL

#define	PLL_COUNT 0x3fU

#define	PLL_INPUT_MAX_HZ 16000000

#define	PLL_INPUT_MIN_HZ 8000000

#define	PLL_OUTPUT_MAX_HZ 192000000

#define	PLL_OUTPUT_MIN_HZ 84000000

#define	PLL_UPLL_HZ 480000000

#define	PLLA_ID 0

#define	UPLL_ID 1
	USB UTMI PLL. More...

Enumerations
enum	pll_source { PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, PLL_NR_SOURCES }
	PLL clock source. More...

Functions
static void	pll_config_init (struct pll_config *p_cfg, enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)

static void	pll_config_read (struct pll_config *p_cfg, uint32_t ul_pll_id)

static void	pll_config_write (const struct pll_config *p_cfg, uint32_t ul_pll_id)

static void	pll_disable (uint32_t ul_pll_id)

static void	pll_enable (const struct pll_config *p_cfg, uint32_t ul_pll_id)

static uint32_t	pll_is_locked (uint32_t ul_pll_id)

Chip-specific PLL characteristics
#define	NR_PLLS 2
	Number of on-chip PLLs. More...

PLL configuration
#define	pll_config_defaults(cfg, pll_id)
	Initialize PLL configuration using default parameters. More...

#define	pll_get_default_rate(pll_id)
	Get the default rate in Hz of pll_id. More...

Interaction with the PLL hardware
static int	pll_wait_for_lock (unsigned int pll_id)
	Wait for PLL pll_id to become locked. More...

static void	pll_enable_source (enum pll_source e_src)
	Enable the source of the pll. More...

static void	pll_enable_config_defaults (unsigned int ul_pll_id)
	Enable the pll with the default configuration. More...

#define CONFIG_PLL1_DIV 0

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL1_MUL 0

Referenced by pll_enable_config_defaults().

#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL

Referenced by pll_enable_config_defaults(), and sysclk_init().

#define NR_PLLS 2

Number of on-chip PLLs.

Referenced by pll_config_read(), pll_config_write(), pll_disable(), pll_enable(), pll_is_locked(), and pll_wait_for_lock().

#define pll_config_defaults	(	cfg,
		pll_id
	)

Value:

pll_config_init(cfg,                                                   \
            CONFIG_PLL##pll_id##_SOURCE,                                   \
            CONFIG_PLL##pll_id##_DIV,                                      \
            CONFIG_PLL##pll_id##_MUL)

Initialize PLL configuration using default parameters.

After this function returns, cfg will contain a configuration which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) times the frequency of CONFIG_PLLx_SOURCE.

Parameters

cfg	The PLL configuration to be initialized.
pll_id	Use defaults for this PLL.

Referenced by sysclk_enable_usb(), and sysclk_init().

#define PLL_COUNT 0x3fU

Referenced by pll_config_init().

#define pll_get_default_rate ( pll_id )

Value:

((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE)                            \
            * CONFIG_PLL##pll_id##_MUL)                                    \
            / CONFIG_PLL##pll_id##_DIV)

Get the default rate in Hz of pll_id.

Referenced by sysclk_get_main_hz().

#define PLL_INPUT_MAX_HZ 16000000

Referenced by pll_config_init().

#define PLL_INPUT_MIN_HZ 8000000

Referenced by pll_config_init().

#define PLL_OUTPUT_MAX_HZ 192000000

Referenced by pll_config_init().

#define PLL_OUTPUT_MIN_HZ 84000000

Referenced by pll_config_init().

#define PLL_UPLL_HZ 480000000

Referenced by sysclk_get_main_hz().

#define PLLA_ID 0

Referenced by pll_config_read(), pll_config_write(), pll_disable(), pll_enable(), and pll_is_locked().

#define UPLL_ID 1

USB UTMI PLL.

enum pll_source

PLL clock source.

Enumerator
PLL_SRC_MAINCK_4M_RC	Internal 4MHz RC oscillator.
PLL_SRC_MAINCK_8M_RC	Internal 8MHz RC oscillator.
PLL_SRC_MAINCK_12M_RC	Internal 12MHz RC oscillator.
PLL_SRC_MAINCK_XTAL	External crystal oscillator.
PLL_SRC_MAINCK_BYPASS	External bypass oscillator.
PLL_NR_SOURCES	Number of PLL sources.

static void pll_config_init	(	struct pll_config *	p_cfg,
		enum pll_source	e_src,
		uint32_t	ul_div,
		uint32_t	ul_mul
	)

inlinestatic

Note: The SAM3X PLL hardware interprets mul as mul+1. For readability the hardware mul+1 is hidden in this implementation. Use mul as mul effective value.

References Assert, pll_config::ctrl, osc_get_rate(), PLL_COUNT, PLL_INPUT_MAX_HZ, PLL_INPUT_MIN_HZ, PLL_NR_SOURCES, PLL_OUTPUT_MAX_HZ, and PLL_OUTPUT_MIN_HZ.

Referenced by pll_enable_config_defaults().